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\chapter{Architecture}
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\chapter{Architecture}
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\section{Block diagram}
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\section{Block diagram}
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The architecture for the full IP core is shown in the Figure~\ref{blockdiagram}. It consists of 2 major parts, the actual
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The architecture for the full IP core is shown in the Figure~\ref{blockdiagram}. It consists of 2 major parts, the actual
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exponentiation core (\verb|mod_sim_exp_core| entity) with a bus interface wrapped around it. In the following sections these
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exponentiation core (\verb|mod_sim_exp_core| entity) with a bus interface wrapped around it. In the following sections these
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different blocks are described in detail.\\
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different blocks are described in detail. The bus interface and the exponentiation core can run on different clock
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frequencies, so they are independent of each other.\\
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\begin{figure}[H]
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\begin{figure}[H]
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\centering
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\centering
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\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=10cm]{pictures/block_diagram.pdf}
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\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=10cm]{pictures/block_diagram.pdf}
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\caption{Block diagram of the Modular Simultaneous Exponentiation IP core}
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\caption{Block diagram of the Modular Simultaneous Exponentiation IP core}
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\label{blockdiagram}
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\label{blockdiagram}
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\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=10cm]{pictures/mod_sim_exp_core.pdf}
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\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=10cm]{pictures/mod_sim_exp_core.pdf}
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\cprotect\caption{\verb|mod_sim_exp_core| structure}
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\cprotect\caption{\verb|mod_sim_exp_core| structure}
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\label{msec_structure}
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\label{msec_structure}
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\end{figure}
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\end{figure}
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The multiplier and control unit operate on the \verb|core_clk| clock frequency and the interface to the operand RAM and
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exponent FIFO operates on the \verb|bus_clk| clock frequency. The transition between the 2 clock domains is mainly
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implemented by the RAM and FIFO. For the remainder, the necessary control signals are synchronised to the
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\verb|bus_clk|. Thus when using the \verb|mod_sim_exp_core|, one can thus assume that al ports are operating on the
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\verb|bus_clk| clock signal.
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\subsection{Multiplier}
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\subsection{Multiplier}
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The kernel of this design is a pipelined Montgomery multiplier. A Montgomery multiplication\cite{MontModMul} allows efficient implementation of a
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The kernel of this design is a pipelined Montgomery multiplier. A Montgomery multiplication\cite{MontModMul} allows efficient implementation of a
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modular multiplication without explicitly carrying out the classical modular reduction step. Right-shift operations ensure that the length of the (intermediate) results does not exceed $n+1$ bits. The result of a Montgomery multiplication is given by~(\ref{eq:mont}):
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modular multiplication without explicitly carrying out the classical modular reduction step. Right-shift operations ensure that the length of the (intermediate) results does not exceed $n+1$ bits. The result of a Montgomery multiplication is given by~(\ref{eq:mont}):
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\begin{align}\label{eq:mont}
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\begin{align}\label{eq:mont}
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r = x \cdot y \cdot R^{-1} \bmod m \hspace{1.5cm}\text{with } R = 2^{n}
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r = x \cdot y \cdot R^{-1} \bmod m \hspace{1.5cm}\text{with } R = 2^{n}
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To store the exponents, there is a FIFO of 32 bit wide. Every 32 bit entry has to be formatted as 16 bit of $e_0$ for the
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To store the exponents, there is a FIFO of 32 bit wide. Every 32 bit entry has to be formatted as 16 bit of $e_0$ for the
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lower part [15:0] and 16 bit of $e_1$ for the higher part [31:16]. Entries have to be pushed in the FIFO starting with the least significant word and ending with the most significant word of the exponents.
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lower part [15:0] and 16 bit of $e_1$ for the higher part [31:16]. Entries have to be pushed in the FIFO starting with the least significant word and ending with the most significant word of the exponents.
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For the FIFO there are 2 styles available. The implementation style depends on the style of the operand memory and it can not be set directly. When the RAM option \verb|"xil_prim"| is chosen, the resulting FIFO will use the FIFO18E1 primitive. It is able to store 512 entries, meaning 2 exponents of each 8192 bit long.
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For the FIFO there are 2 styles available. The implementation style depends on the style of the operand memory and it can not be set directly. When the RAM option \verb|"xil_prim"| is chosen, the resulting FIFO will use the FIFO18E1 primitive. It is able to store 512 entries, meaning 2 exponents of each 8192 bit long.
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When the RAM options \verb|"generic"| or \verb|"asym"| are chosen, a generic FIFO will be implemented. This consist of a symmetric RAM with the control logic for a FIFO. The depth of this generic FIFO is adjustable with the parameter \verb|C_FIFO_DEPTH|.
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When the RAM options \verb|"generic"| or \verb|"asym"| are chosen, a generic FIFO \footnote{This FIFO is a slightly
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The number of RAM blocks for the FIFO is given by (\ref{eq:fifoblocks}), where \verb|RAMBLOCK_SIZE| is the size [bits] of the FPGA's RAM primitive.
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modified version of the generic FIFOs project at OpenCores.org (http://opencores.org/project,generic\_fifos).} will be
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implemented.
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This consist of a dual port symmetric RAM with the control logic for a FIFO. The depth of this generic FIFO is adjustable with the parameter \verb|C_FIFO_AW|. The number of RAM blocks for the FIFO is given by (\ref{eq:fifoblocks}), where
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\verb|RAMBLOCK_SIZE| is the size [bits] of the FPGA's RAM primitive.
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\begin{align}
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\begin{align}
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\left[\left(\mathtt{C\_FIFO\_DEPTH}+1\right) \cdot 32 \right]/ \mathtt{RAMBLOCK\_SIZE} \label{eq:fifoblocks}
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\left[\left(\mathtt{2^{C\_FIFO\_AW}}+1\right) \cdot 32 \right]/ \mathtt{RAMBLOCK\_SIZE} \label{eq:fifoblocks}
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\end{align}
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\end{align}
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\subsection{Control unit}
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\subsection{Control unit}
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The control unit loads in the operands and has full control over the multiplier. For single multiplications, it latches in
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The control unit loads in the operands and has full control over the multiplier. For single multiplications, it latches in
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the $x$ operand, then places the $y$ operand on the bus and starts the multiplier. In case of an exponentiation, the FIFO is
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the $x$ operand, then places the $y$ operand on the bus and starts the multiplier. In case of an exponentiation, the FIFO is
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\begin{tabular}{|l|c|c|p{8cm}|}
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\begin{tabular}{|l|c|c|p{8cm}|}
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\hline
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\hline
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\rowcolor{Gray}
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\rowcolor{Gray}
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\textbf{Port} & \textbf{Width} & \textbf{Direction} & \textbf{Description} \bigstrut\\
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\textbf{Port} & \textbf{Width} & \textbf{Direction} & \textbf{Description} \bigstrut\\
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\hline
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\hline
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\verb|clk| & 1 & in & core clock input \bigstrut\\
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\verb|core_clk| & 1 & in & core clock input, clock signal for the multiplier and control unit \bigstrut\\
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\hline
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\verb|bus_clk| & 1 & in & bus clock input, clock signal for all core IO \bigstrut\\
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\hline
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\hline
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\verb|reset| & 1 & in & reset signal (active high) resets the pipeline, fifo and control logic \bigstrut\\
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\verb|reset| & 1 & in & reset signal (active high) resets the pipeline, fifo and control logic \bigstrut\\
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\hline
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\hline
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\multicolumn{4}{|l|}{\textbf{\textit{operand memory interface}}} \bigstrut\\
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\multicolumn{4}{|l|}{\textbf{\textit{operand memory interface}}} \bigstrut\\
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\hline
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\hline
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\hline
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\hline
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\verb|C_NR_STAGES_LOW| & number of lower stages in the pipeline, defines the bit-width of the lower pipeline part & integer & 32 \bigstrut\\
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\verb|C_NR_STAGES_LOW| & number of lower stages in the pipeline, defines the bit-width of the lower pipeline part & integer & 32 \bigstrut\\
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\hline
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\hline
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\verb|C_SPLIT_PIPELINE| & option to split the pipeline in 2 parts & boolean & true \bigstrut\\
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\verb|C_SPLIT_PIPELINE| & option to split the pipeline in 2 parts & boolean & true \bigstrut\\
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\hline
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\hline
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\verb|C_FIFO_DEPTH| & depth of the generic FIFO, only applicable if \verb|C_MEM_STYLE| = \verb|"generic"| or \verb|"asym"| & integer & 32 \bigstrut\\
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\verb|C_FIFO_AW| & address width of the generic FIFO pointers, FIFO size is equal to $2^{C\_FIFO\_AW} $. & integer & 7 \bigstrut\\
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& only applicable if \verb|C_MEM_STYLE| = \verb|"generic"| or \verb|"asym"| & & \\
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\hline
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\hline
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\verb|C_MEM_STYLE| & select the RAM memory style (3 options): & string & \verb|"generic"| \bigstrut\\
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\verb|C_MEM_STYLE| & select the RAM memory style (3 options): & string & \verb|"generic"| \bigstrut\\
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& \verb|"generic"| : use general 32-bit RAMs & & \\
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& \verb|"generic"| : use general 32-bit RAMs & & \\
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& \verb|"asym"| : use asymmetric RAMs & & \\
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& \verb|"asym"| : use asymmetric RAMs & & \\
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& (For more information see \ref{subsec:RAM_and_FIFO}) & & \\
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& (For more information see \ref{subsec:RAM_and_FIFO}) & & \\
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