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\subsection{Operand RAM and exponent FIFO} \label{subsec:RAM_and_FIFO}
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\subsection{Operand RAM and exponent FIFO} \label{subsec:RAM_and_FIFO}
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The core's RAM is designed to store 4 operands and a modulus. \footnote{This is the default configuration. The number of operands can be increased, but the control logic is only designed to work with the default configuration.} Three (3) options are available for the implementation of the RAM. Setting the parameter \verb|C_MEM_STYLE|, will change the implementation style. All styles try to use the RAM resources available on the FPGA.
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The core's RAM is designed to store 4 operands and a modulus. \footnote{This is the default configuration. The number of operands can be increased, but the control logic is only designed to work with the default configuration.} Three (3) options are available for the implementation of the RAM. Setting the parameter \verb|C_MEM_STYLE|, will change the implementation style. All styles try to use the RAM resources available on the FPGA.
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If the FPGA supports asymmetric RAMs, i.e. with a different read and write width, we suggest that the option \verb|"asym"| is selected. Since the (device specific) RAM blocks are inferred through code, it is imperative to select the right device (\verb|C_DEVICE|), as this inference is different between manufacturers. Currently, only Altera and Xilinx are supported.
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If the FPGA supports asymmetric RAMs, i.e. with a different read and write width, we suggest that the option \verb|"asym"| is selected. Since the (device specific) RAM blocks are inferred through code, it is imperative to select the right device (\verb|C_FPGA_MAN|), as this inference is different between manufacturers. Currently, only Altera and Xilinx are supported.
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If there's no asymmetric RAM support, the option \verb|"generic"| should be selected. This option will work for most FPGAs, but the disadvantage is that it will use more resources than the \verb|"asym"| option. This is because a significant number of LUTs will be used to construct an asymmetric RAM.
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If there's no asymmetric RAM support, the option \verb|"generic"| should be selected. This option will work for most FPGAs, but the disadvantage is that it will use more resources than the \verb|"asym"| option. This is because a significant number of LUTs will be used to construct an asymmetric RAM.
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For both options the size of the RAM adapts dynamically to the chosen pipeline width (\verb|C_NR_BITS_TOTAL|).
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For both options the size of the RAM adapts dynamically to the chosen pipeline width (\verb|C_NR_BITS_TOTAL|).
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& \verb|"asym"| : use asymmetric RAMs & & \\
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& \verb|"asym"| : use asymmetric RAMs & & \\
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& (For more information see \ref{subsec:RAM_and_FIFO}) & & \\
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& (For more information see \ref{subsec:RAM_and_FIFO}) & & \\
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& \verb|"xil_prim"| : use xilinx primitives & &\\
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& \verb|"xil_prim"| : use xilinx primitives & &\\
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& (deprecated) & & \bigstrut[b] \\
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& (deprecated) & & \bigstrut[b] \\
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\hline
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\hline
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\verb|C_DEVICE| & device manufacturer: & & \\
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\verb|C_FPGA_MAN| & device manufacturer: & & \\
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& \verb|"xilinx"| or \verb|"altera"| & string & \verb|"xilinx"| \bigstrut\\
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& \verb|"xilinx"| or \verb|"altera"| & string & \verb|"xilinx"| \bigstrut\\
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\hline
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\hline
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\end{tabular}%
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\end{tabular}%
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\end{center}
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\end{center}
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