Special attention must be taken when writing data to the operands and modulus. The least significant bit of the data has be on the lowest
Special attention must be taken when writing data to the operands and modulus. The least significant bit of the data has be on the lowest
address and the most significant bit on the highest address. A write to the RAM has to happen 1 word at a time, byte writes are not
address and the most significant bit on the highest address. A write to the RAM has to happen 1 word at a time, byte writes are not
supported due to the structure of the RAM.
supported due to the structure of the RAM.
\section{Handling interrupts}
\section{Handling interrupts}
When the embedded processor receives an interrupt signal from this core, it is up to the controlling software to
determine the source of the interrupt by reading out the interrupt flag of the control register.
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When the embedded processor receives an interrupt signal from this core, it is up to the controlling software to determine the source of the interrupt by reading out the interrupt flags of the control register. After handling the interrupt, the appropriate flag must be cleared by user. A reset or core start operation also resets the flags. The interrupt signal is high level sensitive.
