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[/] [mod_sim_exp/] [trunk/] [doc/] [src/] [plb_interface.tex] - Diff between revs 47 and 78
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\rowcolor{Gray}
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\rowcolor{Gray}
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\textbf{Name} & \textbf{Description} & \textbf{VHDL Type} &\textbf{Default Value} \bigstrut\\
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\textbf{Name} & \textbf{Description} & \textbf{VHDL Type} &\textbf{Default Value} \bigstrut\\
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\multicolumn{4}{|l|}{\textit{\textbf{Memory configuration}}} \\
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\multicolumn{4}{|l|}{\textit{\textbf{Memory configuration}}} \\
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\hline
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\hline
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\verb|C_FIFO_DEPTH| & depth of the generic FIFO, only applicable if \verb|C_MEM_STYLE| = \verb|"generic"| or \verb|"asym"| & integer & 32 \bigstrut\\
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\hline
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\verb|C_MEM_STYLE| & the memory structure to use for the RAM, choice between 3 options: & string & \verb|"generic"| \bigstrut\\
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& \verb|"xil_prim"| : use xilinx primitives & & \\
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& \verb|"generic"| : use general 32-bit RAMs & & \\
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& \verb|"asym"| : use asymmetric RAMs & & \\
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& (For more information see \ref{subsec:RAM_and_FIFO}) & & \bigstrut[b] \\
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\hline
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\verb|C_DEVICE| & device manufacturer: & string & \verb|"xilinx"| \\
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& \verb|"xilinx"| or \verb|"altera"| & & \bigstrut\\
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\hline
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\verb|C_BASEADDR| & base address for the IP core's memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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\verb|C_BASEADDR| & base address for the IP core's memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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\hline
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\verb|C_HIGHADDR| & high address for the IP core's memory space & std\_logic\_vector & X"00000000" \bigstrut\\
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\verb|C_HIGHADDR| & high address for the IP core's memory space & std\_logic\_vector & X"00000000" \bigstrut\\
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\hline
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\verb|C_M_BASEADDR| & base address for the modulus memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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\verb|C_M_BASEADDR| & base address for the modulus memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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