Line 653... |
Line 653... |
dina : in std_logic_vector(31 downto 0);
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dina : in std_logic_vector(31 downto 0);
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douta : out std_logic_vector(511 downto 0)
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douta : out std_logic_vector(511 downto 0)
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);
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);
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end component operands_sp;
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end component operands_sp;
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component sys_stage is
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generic(
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width : integer := 32 -- width of the stage
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);
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port(
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-- clock input
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core_clk : in std_logic;
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-- modulus and y operand input (width)-bit
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y : in std_logic_vector((width-1) downto 0);
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m : in std_logic_vector((width) downto 0);
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my_cin : in std_logic;
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my_cout : out std_logic;
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-- q and x operand input (serial input)
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xin : in std_logic;
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qin : in std_logic;
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-- q and x operand output (serial output)
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xout : out std_logic;
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qout : out std_logic;
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-- msb input (lsb from next stage, for shift right operation)
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a_msb : in std_logic;
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a_0 : out std_logic;
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-- carry out(clocked) and in
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cin : in std_logic;
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cout : out std_logic;
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-- reduction adder carry's
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red_cin : in std_logic;
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red_cout : out std_logic;
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-- control singals
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start : in std_logic;
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reset : in std_logic;
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done : out std_logic;
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-- result out
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r_sel : in std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result
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r : out std_logic_vector((width-1) downto 0)
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);
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end component sys_stage;
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--------------------------------------------------------------------
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-- sys_pipeline
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--------------------------------------------------------------------
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-- the pipelined systolic array for a montgommery multiplier
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-- contains a structural description of the pipeline using the systolic stages
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--
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component sys_pipeline is
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generic(
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n : integer := 1536; -- width of the operands (# bits)
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t : integer := 192; -- total number of stages (divider of n) >= 2
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tl : integer := 64 -- lower number of stages (best take t = sqrt(n))
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);
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port(
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-- clock input
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core_clk : in std_logic;
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-- modulus and y opperand input (n)-bit
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y : in std_logic_vector((n-1) downto 0);
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m : in std_logic_vector((n-1) downto 0);
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-- x operand input (serial)
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xi : in std_logic;
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next_x : out std_logic; -- next x operand bit
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-- control signals
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start : in std_logic; -- start multiplier
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reset : in std_logic;
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p_sel : in std_logic_vector(1 downto 0); -- select which piece of the pipeline will be used
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-- result out
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r : out std_logic_vector((n-1) downto 0)
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);
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end component sys_pipeline;
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component mont_multiplier is
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generic (
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n : integer := 1536; -- width of the operands
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nr_stages : integer := 96; -- total number of stages
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stages_low : integer := 32 -- lower number of stages
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);
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port (
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-- clock input
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core_clk : in std_logic;
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-- operand inputs
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xy : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
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m : in std_logic_vector((n-1) downto 0); -- modulus
|
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-- result output
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r : out std_logic_vector((n-1) downto 0); -- result
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-- control signals
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start : in std_logic;
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reset : in std_logic;
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p_sel : in std_logic_vector(1 downto 0);
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load_x : in std_logic;
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ready : out std_logic
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);
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end component mont_multiplier;
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end package mod_sim_exp_pkg;
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end package mod_sim_exp_pkg;
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