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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Diff between revs 25 and 30
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Rev 30 |
Line 691... |
Line 691... |
r_sel : in std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result
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r_sel : in std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result
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r : out std_logic_vector((width-1) downto 0)
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r : out std_logic_vector((width-1) downto 0)
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);
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);
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end component sys_stage;
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end component sys_stage;
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--------------------------------------------------------------------
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-- sys_last_cell_logic
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--------------------------------------------------------------------
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-- logic needed as the last piece in the systolic array pipeline
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-- calculates the last 2 bits of the cell_result and finishes the reduction
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-- also generates the result selection signal
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--
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component sys_last_cell_logic is
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port (
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core_clk : in std_logic; -- clock input
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reset : in std_logic;
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a_0 : out std_logic; -- a_msb for last stage
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cin : in std_logic; -- cout from last stage
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red_cin : in std_logic; -- red_cout from last stage
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r_sel : out std_logic; -- result selection bit
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start : in std_logic -- done signal from last stage
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);
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end component sys_last_cell_logic;
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- sys_pipeline
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-- sys_pipeline
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- the pipelined systolic array for a montgommery multiplier
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-- the pipelined systolic array for a montgommery multiplier
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