Line 200... |
Line 200... |
r : out std_logic_vector((width-1) downto 0)
|
r : out std_logic_vector((width-1) downto 0)
|
);
|
);
|
end component adder_block;
|
end component adder_block;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- adder_n
|
|
--------------------------------------------------------------------
|
|
-- n-bit adder using adder blocks. works in stages, to prevent
|
|
-- large carry propagation.
|
|
-- Result avaiable after (width/block_width) clock cycles
|
|
--
|
|
component adder_n is
|
|
generic (
|
|
width : integer := 1536; -- adder operands width
|
|
block_width : integer := 8 -- adder blocks size
|
|
);
|
|
port (
|
|
-- clock input
|
|
core_clk : in std_logic;
|
|
-- adder input operands (width)-bit
|
|
a : in std_logic_vector((width-1) downto 0);
|
|
b : in std_logic_vector((width-1) downto 0);
|
|
-- carry in, out
|
|
cin : in std_logic;
|
|
cout : out std_logic;
|
|
-- adder output result (width)-bit
|
|
r : out std_logic_vector((width-1) downto 0)
|
|
);
|
|
end component adder_n;
|
|
|
|
--------------------------------------------------------------------
|
|
-- standard_cell_block
|
-- standard_cell_block
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- a standard cell block of (width)-bit for the montgommery multiplier
|
-- a standard cell block of (width)-bit for the montgommery multiplier
|
-- systolic array
|
-- systolic array
|
--
|
--
|
Line 254... |
Line 228... |
r : out std_logic_vector((width-1) downto 0)
|
r : out std_logic_vector((width-1) downto 0)
|
);
|
);
|
end component standard_cell_block;
|
end component standard_cell_block;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- standard_stage
|
|
--------------------------------------------------------------------
|
|
-- standard stage for use in the montgommery multiplier pipeline
|
|
-- the result is available after 1 clock cycle
|
|
--
|
|
component standard_stage is
|
|
generic(
|
|
width : integer := 32
|
|
);
|
|
port(
|
|
-- clock input
|
|
core_clk : in std_logic;
|
|
-- modulus and y operand input (width)-bit
|
|
my : in std_logic_vector((width-1) downto 0);
|
|
y : in std_logic_vector((width-1) downto 0);
|
|
m : in std_logic_vector((width-1) downto 0);
|
|
-- q and x operand input (serial input)
|
|
xin : in std_logic;
|
|
qin : in std_logic;
|
|
-- q and x operand output (serial output)
|
|
xout : out std_logic;
|
|
qout : out std_logic;
|
|
-- msb input (lsb from next stage, for shift right operation)
|
|
a_msb : in std_logic;
|
|
-- carry out(clocked) and in
|
|
cin : in std_logic;
|
|
cout : out std_logic;
|
|
-- control singals
|
|
start : in std_logic;
|
|
reset : in std_logic;
|
|
done : out std_logic;
|
|
-- result out
|
|
r : out std_logic_vector((width-1) downto 0)
|
|
);
|
|
end component standard_stage;
|
|
|
|
--------------------------------------------------------------------
|
|
-- first_stage
|
|
--------------------------------------------------------------------
|
|
-- first stage for use in the montgommery multiplier pipeline
|
|
-- generates the q signal for all following stages
|
|
-- the result is available after 1 clock cycle
|
|
--
|
|
component first_stage is
|
|
generic(
|
|
width : integer := 16 -- must be the same as width of the standard stage
|
|
);
|
|
port(
|
|
-- clock input
|
|
core_clk : in std_logic;
|
|
-- modulus and y operand input (width+1)-bit
|
|
my : in std_logic_vector((width) downto 0);
|
|
y : in std_logic_vector((width) downto 0);
|
|
m : in std_logic_vector((width) downto 0);
|
|
-- x operand input (serial input)
|
|
xin : in std_logic;
|
|
-- q and x operand output (serial output)
|
|
xout : out std_logic;
|
|
qout : out std_logic;
|
|
-- msb input (lsb from next stage, for shift right operation)
|
|
a_msb : in std_logic;
|
|
-- carry out
|
|
cout : out std_logic;
|
|
-- control signals
|
|
start : in std_logic;
|
|
reset : in std_logic;
|
|
done : out std_logic;
|
|
-- result out
|
|
r : out std_logic_vector((width-1) downto 0)
|
|
);
|
|
end component first_stage;
|
|
|
|
--------------------------------------------------------------------
|
|
-- last_stage
|
|
--------------------------------------------------------------------
|
|
-- last stage for use in the montgommery multiplier pipeline
|
|
-- the result is available after 1 clock cycle
|
|
--
|
|
component last_stage is
|
|
generic(
|
|
width : integer := 16 -- must be the same as width of the standard stage
|
|
);
|
|
port(
|
|
-- clock input
|
|
core_clk : in std_logic;
|
|
-- modulus and y operand input (width(-1))-bit
|
|
my : in std_logic_vector((width-1) downto 0);
|
|
y : in std_logic_vector((width-2) downto 0);
|
|
m : in std_logic_vector((width-2) downto 0);
|
|
-- q and x operand input (serial input)
|
|
xin : in std_logic;
|
|
qin : in std_logic;
|
|
-- carry in
|
|
cin : in std_logic;
|
|
-- control signals
|
|
start : in std_logic;
|
|
reset : in std_logic;
|
|
-- result out
|
|
r : out std_logic_vector((width+1) downto 0)
|
|
);
|
|
end component last_stage;
|
|
|
|
--------------------------------------------------------------------
|
|
-- counter_sync
|
-- counter_sync
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- counter with synchronous count enable. It generates an
|
-- counter with synchronous count enable. It generates an
|
-- overflow when max_value is reached
|
-- overflow when max_value is reached
|
--
|
--
|
Line 426... |
Line 297... |
xi : out std_logic
|
xi : out std_logic
|
);
|
);
|
end component x_shift_reg;
|
end component x_shift_reg;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- systolic_pipeline
|
|
--------------------------------------------------------------------
|
|
-- systolic pipeline implementation of the montgommery multiplier
|
|
-- devides the pipeline into 2 parts, so 3 operand widths are supported
|
|
--
|
|
-- p_sel:
|
|
-- 01 = lower part
|
|
-- 10 = upper part
|
|
-- 11 = full range
|
|
component systolic_pipeline is
|
|
generic(
|
|
n : integer := 1536; -- width of the operands (# bits)
|
|
t : integer := 192; -- total number of stages (divider of n) >= 2
|
|
tl : integer := 64 -- lower number of stages (best take t = sqrt(n))
|
|
);
|
|
port(
|
|
-- clock input
|
|
core_clk : in std_logic;
|
|
-- modulus and y opperand input (n)-bit
|
|
my : in std_logic_vector((n) downto 0); -- m+y
|
|
y : in std_logic_vector((n-1) downto 0);
|
|
m : in std_logic_vector((n-1) downto 0);
|
|
-- x operand input (serial)
|
|
xi : in std_logic;
|
|
-- control signals
|
|
start : in std_logic; -- start multiplier
|
|
reset : in std_logic;
|
|
p_sel : in std_logic_vector(1 downto 0); -- select which piece of the multiplier will be used
|
|
ready : out std_logic; -- multiplication ready
|
|
next_x : out std_logic; -- next x operand bit
|
|
-- result out
|
|
r : out std_logic_vector((n+1) downto 0)
|
|
);
|
|
end component systolic_pipeline;
|
|
|
|
--------------------------------------------------------------------
|
|
-- mont_mult_sys_pipeline
|
|
--------------------------------------------------------------------
|
|
-- Structural description of the montgommery multiply pipeline
|
|
-- contains the x operand shift register, my adder, the pipeline and
|
|
-- reduction adder. To do a multiplication, the following actions must take place:
|
|
--
|
|
-- * load in the x operand in the shift register using the xy bus and load_x
|
|
-- * place the y operand on the xy bus for the rest of the operation
|
|
-- * generate a start pulse of 1 clk cycle long on start
|
|
-- * wait for ready signal
|
|
-- * result is avaiable on the r bus
|
|
--
|
|
component mont_mult_sys_pipeline is
|
|
generic (
|
|
n : integer := 1536; -- width of the operands
|
|
t : integer := 96; -- total number of stages
|
|
tl : integer := 32 -- lower number of stages
|
|
);
|
|
port (
|
|
-- clock input
|
|
core_clk : in std_logic;
|
|
-- operand inputs
|
|
xy : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
|
|
m : in std_logic_vector((n-1) downto 0); -- modulus
|
|
-- result output
|
|
r : out std_logic_vector((n-1) downto 0); -- result
|
|
-- control signals
|
|
start : in std_logic;
|
|
reset : in std_logic;
|
|
p_sel : in std_logic_vector(1 downto 0);
|
|
load_x : in std_logic;
|
|
ready : out std_logic
|
|
);
|
|
end component mont_mult_sys_pipeline;
|
|
|
|
--------------------------------------------------------------------
|
|
-- mod_sim_exp_core
|
-- mod_sim_exp_core
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- toplevel of the modular simultaneous exponentiation core
|
-- toplevel of the modular simultaneous exponentiation core
|
-- contains an operand and modulus ram, multiplier, an exponent fifo
|
-- contains an operand and modulus ram, multiplier, an exponent fifo
|
-- and control logic
|
-- and control logic
|