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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- operand_mem_gen ----
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---- operand_mem ----
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---- ----
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---- ----
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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- BRAM memory and logic to the store 4 (1536-bit) operands ----
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---- RAM memory and logic to the store operands and the ----
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---- and the modulus for the montgomery multiplier ----
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---- modulus for the montgomery multiplier, the user has a ----
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---- choise between 3 memory styles, more detail in the ----
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---- documentation ----
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---- ----
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---- ----
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---- Dependencies: ----
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---- Dependencies: ----
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---- - operand_ram ----
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---- - modulus_ram ----
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---- - operand_ram_gen ----
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---- - operand_ram_gen ----
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---- - modulus_ram_gen ----
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---- - modulus_ram_gen ----
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---- - operand_ram_asym ----
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---- - modulus_ram_asym ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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---- ----
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-- '0': operands
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-- '0': operands
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-- bits: (highest-1)-log2(width/32) -> operand_in_sel in case of highest bit = '0'
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-- bits: (highest-1)-log2(width/32) -> operand_in_sel in case of highest bit = '0'
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-- modulus_in_sel in case of highest bit = '1'
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-- modulus_in_sel in case of highest bit = '1'
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-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
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-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
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--
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--
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entity operand_mem_gen is
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entity operand_mem is
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generic(
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generic(
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width : integer := 1536; -- width of the operands
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width : integer := 1536; -- width of the operands
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nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m
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nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m
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nr_m : integer := 2 -- nr of modulus storages
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nr_m : integer := 2; -- nr of modulus storages
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mem_style : string := "asym"; -- xil_prim, generic, asym are valid options
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device : string := "altera" -- xilinx, altera are valid options
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);
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);
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port(
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port(
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-- system clock
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-- system clock
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clk : in std_logic;
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clk : in std_logic;
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-- data interface (plb side)
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-- data interface (plb side)
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Line 91... |
load_result : in std_logic;
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load_result : in std_logic;
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result_dest_op : in std_logic_vector(log2(nr_op)-1 downto 0);
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result_dest_op : in std_logic_vector(log2(nr_op)-1 downto 0);
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collision : out std_logic;
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collision : out std_logic;
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modulus_sel : in std_logic_vector(log2(nr_m)-1 downto 0)
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modulus_sel : in std_logic_vector(log2(nr_m)-1 downto 0)
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);
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);
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end operand_mem_gen;
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end operand_mem;
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architecture Behavioral of operand_mem_gen is
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architecture structural of operand_mem is
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-- constants
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constant wordaddr_aw : integer := log2(width/32);
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constant wordaddr_aw : integer := log2(width/32);
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constant opaddr_aw : integer := log2(nr_op);
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constant opaddr_aw : integer := log2(nr_op);
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constant maddr_aw : integer := log2(nr_m);
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constant maddr_aw : integer := log2(nr_m);
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constant total_aw : integer := 1+opaddr_aw+wordaddr_aw;
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constant total_aw : integer := 1+opaddr_aw+wordaddr_aw;
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-- internal signals
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signal xy_data_i : std_logic_vector(31 downto 0);
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signal xy_data_i : std_logic_vector(31 downto 0);
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signal xy_addr_i : std_logic_vector(wordaddr_aw-1 downto 0);
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signal xy_addr_i : std_logic_vector(wordaddr_aw-1 downto 0);
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signal operand_in_sel_i : std_logic_vector(opaddr_aw-1 downto 0);
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signal operand_in_sel_i : std_logic_vector(opaddr_aw-1 downto 0);
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signal modulus_in_sel_i : std_logic_vector(maddr_aw-1 downto 0);
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signal modulus_in_sel_i : std_logic_vector(maddr_aw-1 downto 0);
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operand_in_sel_i <= rw_address(total_aw-2 downto wordaddr_aw);
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operand_in_sel_i <= rw_address(total_aw-2 downto wordaddr_aw);
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modulus_in_sel_i <= rw_address(wordaddr_aw+maddr_aw-1 downto wordaddr_aw);
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modulus_in_sel_i <= rw_address(wordaddr_aw+maddr_aw-1 downto wordaddr_aw);
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xy_data_i <= data_in;
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xy_data_i <= data_in;
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m_data_i <= data_in;
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m_data_i <= data_in;
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-- select right memory with highest address bit
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load_op <= write_enable when (rw_address(total_aw-1) = '0') else '0';
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load_op <= write_enable when (rw_address(total_aw-1) = '0') else '0';
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load_m <= write_enable when (rw_address(total_aw-1) = '1') else '0';
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load_m <= write_enable when (rw_address(total_aw-1) = '1') else '0';
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xil_prim_RAM : if mem_style="xil_prim" generate
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-- xy operand storage
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-- xy operand storage
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xy_ram : operand_ram_gen
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xy_ram_xil : operand_ram
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port map(
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clk => clk,
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collision => collision,
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operand_addr => xy_addr_i,
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operand_in => xy_data_i,
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operand_in_sel => operand_in_sel_i,
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result_out => data_out,
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write_operand => load_op,
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operand_out => xy_out,
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operand_out_sel => op_sel,
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result_dest_op => result_dest_op,
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write_result => load_result,
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result_in => result_in
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);
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-- modulus storage
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m_ram_xil : modulus_ram
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port map(
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clk => clk,
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modulus_addr => m_addr_i,
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write_modulus => load_m,
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modulus_in => m_data_i,
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modulus_out => m
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);
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end generate;
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gen_RAM : if mem_style="generic" generate
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-- xy operand storage
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xy_ram_gen : operand_ram_gen
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generic map(
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generic map(
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width => width,
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width => width,
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depth => nr_op
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depth => nr_op
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)
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)
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port map(
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port map(
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write_result => load_result,
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write_result => load_result,
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result_in => result_in
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result_in => result_in
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);
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);
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-- modulus storage
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-- modulus storage
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m_ram : modulus_ram_gen
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m_ram_gen : modulus_ram_gen
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generic map(
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generic map(
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width => width,
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width => width,
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depth => nr_m
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depth => nr_m
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)
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)
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port map(
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port map(
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write_modulus => load_m,
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write_modulus => load_m,
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modulus_in => m_data_i,
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modulus_in => m_data_i,
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modulus_out => m,
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modulus_out => m,
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modulus_sel => modulus_sel
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modulus_sel => modulus_sel
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);
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);
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end generate;
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asym_RAM : if mem_style="asym" generate
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-- xy operand storage
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xy_ram_asym : operand_ram_asym
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generic map(
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width => width,
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depth => nr_op,
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device => device
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)
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port map(
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clk => clk,
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collision => collision,
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operand_addr => xy_addr_i,
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operand_in => xy_data_i,
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operand_in_sel => operand_in_sel_i,
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result_out => data_out,
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write_operand => load_op,
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operand_out => xy_out,
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operand_out_sel => op_sel,
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result_dest_op => result_dest_op,
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write_result => load_result,
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result_in => result_in
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);
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-- modulus storage
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m_ram_asym : modulus_ram_asym
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generic map(
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width => width,
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depth => nr_m,
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device => device
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)
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port map(
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clk => clk,
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modulus_in_sel => modulus_in_sel_i,
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modulus_addr => m_addr_i,
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write_modulus => load_m,
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modulus_in => m_data_i,
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modulus_out => m,
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modulus_sel => modulus_sel
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);
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end generate;
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end Behavioral;
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end structural;
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No newline at end of file
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No newline at end of file
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