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use proc_common_v3_00_a.proc_common_pkg.all;
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use proc_common_v3_00_a.proc_common_pkg.all;
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-- DO NOT EDIT ABOVE THIS LINE --------------------
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-- DO NOT EDIT ABOVE THIS LINE --------------------
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--USER libraries added here
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--USER libraries added here
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_core_pkg.all;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Entity section
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-- Entity section
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Definition of Generics:
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-- Definition of Generics:
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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architecture IMP of user_logic is
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architecture IMP of user_logic is
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--USER signal declarations added here, as needed for user logic
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--USER signal declarations added here, as needed for user logic
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component multiplier_core
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port( clk : in std_logic;
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reset : in std_logic;
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-- operand memory interface (plb shared memory)
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write_enable : in std_logic;
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data_in : in std_logic_vector (31 downto 0);
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rw_address : in std_logic_vector (8 downto 0);
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data_out : out std_logic_vector (31 downto 0);
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collision : out std_logic;
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-- op_sel fifo interface
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fifo_din : in std_logic_vector (31 downto 0);
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fifo_push : in std_logic;
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fifo_full : out std_logic;
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fifo_nopush : out std_logic;
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-- ctrl signals
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start : in std_logic;
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run_auto : in std_logic;
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ready : out std_logic;
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x_sel_single : in std_logic_vector (1 downto 0);
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y_sel_single : in std_logic_vector (1 downto 0);
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dest_op_single : in std_logic_vector (1 downto 0);
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p_sel : in std_logic_vector (1 downto 0);
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calc_time : out std_logic
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);
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end component;
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------------------------------------------------------------------
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------------------------------------------------------------------
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-- Signals for multiplier core slave model s/w accessible register
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-- Signals for multiplier core slave model s/w accessible register
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------------------------------------------------------------------
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------------------------------------------------------------------
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signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
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signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
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core_y_sel_single <= slv_reg0(6 to 7);
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core_y_sel_single <= slv_reg0(6 to 7);
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------------------------------------------
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------------------------------------------
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-- Multiplier core instance
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-- Multiplier core instance
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------------------------------------------
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------------------------------------------
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the_multiplier: multiplier_core
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the_multiplier: mod_sim_exp_core
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port map( clk => Bus2IP_Clk, -- v
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port map( clk => Bus2IP_Clk, -- v
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reset => Bus2IP_Reset, -- v
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reset => Bus2IP_Reset, -- v
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-- operand memory interface (plb shared memory)
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-- operand memory interface (plb shared memory)
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write_enable => core_write_enable,
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write_enable => core_write_enable,
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data_in => core_data_in,
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data_in => core_data_in,
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