Line 98... |
Line 98... |
-- Multiplier parameters
|
-- Multiplier parameters
|
C_NR_BITS_TOTAL : integer := 1536;
|
C_NR_BITS_TOTAL : integer := 1536;
|
C_NR_STAGES_TOTAL : integer := 96;
|
C_NR_STAGES_TOTAL : integer := 96;
|
C_NR_STAGES_LOW : integer := 32;
|
C_NR_STAGES_LOW : integer := 32;
|
C_SPLIT_PIPELINE : boolean := true;
|
C_SPLIT_PIPELINE : boolean := true;
|
|
C_FIFO_DEPTH : integer := 32;
|
-- ADD USER GENERICS ABOVE THIS LINE ---------------
|
-- ADD USER GENERICS ABOVE THIS LINE ---------------
|
|
|
-- DO NOT EDIT BELOW THIS LINE ---------------------
|
-- DO NOT EDIT BELOW THIS LINE ---------------------
|
-- Bus protocol parameters, do not add to or delete
|
-- Bus protocol parameters, do not add to or delete
|
C_SLV_AWIDTH : integer := 32;
|
C_SLV_AWIDTH : integer := 32;
|
Line 181... |
Line 182... |
signal core_p_sel : std_logic_vector(1 downto 0);
|
signal core_p_sel : std_logic_vector(1 downto 0);
|
signal core_dest_op_single : std_logic_vector(1 downto 0);
|
signal core_dest_op_single : std_logic_vector(1 downto 0);
|
signal core_x_sel_single : std_logic_vector(1 downto 0);
|
signal core_x_sel_single : std_logic_vector(1 downto 0);
|
signal core_y_sel_single : std_logic_vector(1 downto 0);
|
signal core_y_sel_single : std_logic_vector(1 downto 0);
|
signal core_flags : std_logic_vector(15 downto 0);
|
signal core_flags : std_logic_vector(15 downto 0);
|
|
signal core_modulus_sel : std_logic_vector(0 downto 0);
|
|
|
------------------------------------------------------------------
|
------------------------------------------------------------------
|
-- Signals for multiplier core memory space
|
-- Signals for multiplier core memory space
|
------------------------------------------------------------------
|
------------------------------------------------------------------
|
signal mem_address : std_logic_vector(0 to 5);
|
signal mem_address : std_logic_vector(0 to 5);
|
Line 382... |
Line 384... |
mem_ip2bus_data <= core_data_out;
|
mem_ip2bus_data <= core_data_out;
|
|
|
------------------------------------------
|
------------------------------------------
|
-- Map slv_reg0 bits to core control signals
|
-- Map slv_reg0 bits to core control signals
|
------------------------------------------
|
------------------------------------------
|
core_start <= slv_reg0(8);
|
|
core_exp_m <= slv_reg0(9);
|
|
core_p_sel <= slv_reg0(0 to 1);
|
core_p_sel <= slv_reg0(0 to 1);
|
core_dest_op_single <= slv_reg0(2 to 3);
|
core_dest_op_single <= slv_reg0(2 to 3);
|
core_x_sel_single <= slv_reg0(4 to 5);
|
core_x_sel_single <= slv_reg0(4 to 5);
|
core_y_sel_single <= slv_reg0(6 to 7);
|
core_y_sel_single <= slv_reg0(6 to 7);
|
|
core_start <= slv_reg0(8);
|
|
core_exp_m <= slv_reg0(9);
|
|
core_modulus_sel <= slv_reg0(10 to 10);
|
|
|
------------------------------------------
|
------------------------------------------
|
-- Multiplier core instance
|
-- Multiplier core instance
|
------------------------------------------
|
------------------------------------------
|
the_multiplier: mod_sim_exp_core
|
the_multiplier: mod_sim_exp_core
|
generic map(
|
generic map(
|
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
|
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
|
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
|
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
|
C_NR_STAGES_LOW => C_NR_STAGES_LOW,
|
C_NR_STAGES_LOW => C_NR_STAGES_LOW,
|
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE
|
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
|
|
C_NR_OP => 4,
|
|
C_NR_M => 2,
|
|
C_FIFO_DEPTH => C_FIFO_DEPTH
|
)
|
)
|
port map(
|
port map(
|
clk => Bus2IP_Clk,
|
clk => Bus2IP_Clk,
|
reset => Bus2IP_Reset,
|
reset => Bus2IP_Reset,
|
-- operand memory interface (plb shared memory)
|
-- operand memory interface (plb shared memory)
|
Line 421... |
Line 428... |
ready => core_ready,
|
ready => core_ready,
|
x_sel_single => core_x_sel_single,
|
x_sel_single => core_x_sel_single,
|
y_sel_single => core_y_sel_single,
|
y_sel_single => core_y_sel_single,
|
dest_op_single => core_dest_op_single,
|
dest_op_single => core_dest_op_single,
|
p_sel => core_p_sel,
|
p_sel => core_p_sel,
|
calc_time => calc_time
|
calc_time => calc_time,
|
|
modulus_sel => core_modulus_sel
|
);
|
);
|
|
|
|
|
------------------------------------------
|
------------------------------------------
|
-- Drive IP to Bus signals
|
-- Drive IP to Bus signals
|