Line 184... |
Line 184... |
signal core_p_sel : std_logic_vector(1 downto 0);
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signal core_p_sel : std_logic_vector(1 downto 0);
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signal core_dest_op_single : std_logic_vector(1 downto 0);
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signal core_dest_op_single : std_logic_vector(1 downto 0);
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signal core_x_sel_single : std_logic_vector(1 downto 0);
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signal core_x_sel_single : std_logic_vector(1 downto 0);
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signal core_y_sel_single : std_logic_vector(1 downto 0);
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signal core_y_sel_single : std_logic_vector(1 downto 0);
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signal core_flags : std_logic_vector(15 downto 0);
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signal core_flags : std_logic_vector(15 downto 0);
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signal core_modulus_sel : std_logic_vector(0 downto 0);
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signal core_modulus_sel : std_logic;
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------------------------------------------------------------------
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------------------------------------------------------------------
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-- Signals for multiplier core memory space
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-- Signals for multiplier core memory space
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------------------------------------------------------------------
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------------------------------------------------------------------
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signal mem_address : std_logic_vector(0 to 5);
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signal mem_address : std_logic_vector(0 to 5);
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core_dest_op_single <= slv_reg0(2 to 3);
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core_dest_op_single <= slv_reg0(2 to 3);
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core_x_sel_single <= slv_reg0(4 to 5);
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core_x_sel_single <= slv_reg0(4 to 5);
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core_y_sel_single <= slv_reg0(6 to 7);
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core_y_sel_single <= slv_reg0(6 to 7);
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core_start <= slv_reg0(8);
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core_start <= slv_reg0(8);
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core_exp_m <= slv_reg0(9);
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core_exp_m <= slv_reg0(9);
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core_modulus_sel <= slv_reg0(10 to 10);
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core_modulus_sel <= slv_reg0(10);
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------------------------------------------
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------------------------------------------
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-- Multiplier core instance
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-- Multiplier core instance
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------------------------------------------
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------------------------------------------
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the_multiplier: mod_sim_exp_core
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the_multiplier: mod_sim_exp_core
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