| Line 100... |
Line 100... |
C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_LOW : integer := 32;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true;
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C_SPLIT_PIPELINE : boolean := true;
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C_FIFO_DEPTH : integer := 32;
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C_FIFO_DEPTH : integer := 32;
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C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options
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C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options
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C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options
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C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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-- ADD USER GENERICS ABOVE THIS LINE ---------------
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-- ADD USER GENERICS ABOVE THIS LINE ---------------
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|
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- Bus protocol parameters, do not add to or delete
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-- Bus protocol parameters, do not add to or delete
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C_SLV_AWIDTH : integer := 32;
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C_SLV_AWIDTH : integer := 32;
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| Line 406... |
Line 406... |
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_FIFO_DEPTH => C_FIFO_DEPTH,
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C_FIFO_DEPTH => C_FIFO_DEPTH,
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C_MEM_STYLE => C_MEM_STYLE,
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C_MEM_STYLE => C_MEM_STYLE,
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C_DEVICE => C_DEVICE
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C_FPGA_MAN => C_FPGA_MAN
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)
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)
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port map(
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port map(
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clk => Bus2IP_Clk,
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clk => Bus2IP_Clk,
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reset => Bus2IP_Reset,
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reset => Bus2IP_Reset,
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-- operand memory interface (plb shared memory)
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-- operand memory interface (plb shared memory)
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