| Line 98... |
Line 98... |
-- Multiplier parameters
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-- Multiplier parameters
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_LOW : integer := 32;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true;
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C_SPLIT_PIPELINE : boolean := true;
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C_FIFO_DEPTH : integer := 32;
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C_FIFO_AW : integer := 7;
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C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options
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C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options
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C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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-- ADD USER GENERICS ABOVE THIS LINE ---------------
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-- ADD USER GENERICS ABOVE THIS LINE ---------------
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|
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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| Line 117... |
Line 117... |
port
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port
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(
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(
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-- ADD USER PORTS BELOW THIS LINE ------------------
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-- ADD USER PORTS BELOW THIS LINE ------------------
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--USER ports added here
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--USER ports added here
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calc_time : out std_logic;
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calc_time : out std_logic;
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-- ctrl_sigs : out std_logic_vector( downto );
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core_clk : in std_logic;
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-- ADD USER PORTS ABOVE THIS LINE ------------------
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-- ADD USER PORTS ABOVE THIS LINE ------------------
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|
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- Bus protocol ports, do not add to or delete
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-- Bus protocol ports, do not add to or delete
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Bus2IP_Clk : in std_logic;
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Bus2IP_Clk : in std_logic;
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| Line 404... |
Line 404... |
generic map(
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generic map(
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C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_FIFO_DEPTH => C_FIFO_DEPTH,
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C_FIFO_AW => C_FIFO_AW,
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C_MEM_STYLE => C_MEM_STYLE,
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C_MEM_STYLE => C_MEM_STYLE,
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C_FPGA_MAN => C_FPGA_MAN
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C_FPGA_MAN => C_FPGA_MAN
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)
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)
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port map(
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port map(
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clk => Bus2IP_Clk,
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core_clk => core_clk,
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bus_clk => Bus2IP_Clk,
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reset => Bus2IP_Reset,
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reset => Bus2IP_Reset,
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-- operand memory interface (plb shared memory)
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-- operand memory interface (plb shared memory)
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write_enable => core_write_enable,
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write_enable => core_write_enable,
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data_in => core_data_in,
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data_in => core_data_in,
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rw_address => core_rw_address,
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rw_address => core_rw_address,
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