| Line 60... |
Line 60... |
rddepth : integer := 4; -- nr of 32-bit words
|
rddepth : integer := 4; -- nr of 32-bit words
|
wrwidth : integer := 2; -- write width, must be smaller than or equal to 32
|
wrwidth : integer := 2; -- write width, must be smaller than or equal to 32
|
device : string := "xilinx" -- device template to use
|
device : string := "xilinx" -- device template to use
|
);
|
);
|
port (
|
port (
|
|
clk : in std_logic;
|
-- write port
|
-- write port
|
clkA : in std_logic;
|
waddr : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0);
|
waddrA : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0);
|
we : in std_logic;
|
weA : in std_logic;
|
din : in std_logic_vector(wrwidth-1 downto 0);
|
dinA : in std_logic_vector(wrwidth-1 downto 0);
|
|
-- read port
|
-- read port
|
clkB : in std_logic;
|
raddr : in std_logic_vector(log2(rddepth)-1 downto 0);
|
raddrB : in std_logic_vector(log2(rddepth)-1 downto 0);
|
dout : out std_logic_vector(31 downto 0)
|
doutB : out std_logic_vector(31 downto 0)
|
|
);
|
);
|
end dpram_asym;
|
end dpram_asym;
|
|
|
architecture behavorial of dpram_asym is
|
architecture behavorial of dpram_asym is
|
-- constants
|
-- constants
|
| Line 81... |
Line 80... |
begin
|
begin
|
|
|
xilinx_device : if device="xilinx" generate
|
xilinx_device : if device="xilinx" generate
|
-- the memory
|
-- the memory
|
type ram_type is array (wrdepth-1 downto 0) of std_logic_vector (wrwidth-1 downto 0);
|
type ram_type is array (wrdepth-1 downto 0) of std_logic_vector (wrwidth-1 downto 0);
|
shared variable RAM : ram_type := (others => (others => '0'));
|
signal RAM : ram_type := (others => (others => '0'));
|
|
|
-- xilinx constraint to use blockram resources
|
-- xilinx constraint to use blockram resources
|
attribute ram_style : string;
|
attribute ram_style : string;
|
attribute ram_style of RAM:variable is "block";
|
attribute ram_style of ram:signal is "block";
|
begin
|
begin
|
-- Write port A
|
process (clk)
|
process (clkA)
|
|
begin
|
begin
|
if rising_edge(clkA) then
|
if (clk'event and clk = '1') then
|
if (weA = '1') then
|
if (we = '1') then
|
RAM(conv_integer(waddrA)) := dinA;
|
RAM(conv_integer(waddr)) <= din;
|
end if;
|
end if;
|
end if;
|
|
end process;
|
|
|
|
-- Read port B
|
|
process (clkB)
|
|
begin
|
|
if rising_edge(clkB) then
|
|
for i in 0 to R-1 loop
|
for i in 0 to R-1 loop
|
doutB((i+1)*wrwidth-1 downto i*wrwidth)
|
dout((i+1)*wrwidth-1 downto i*wrwidth)
|
<= RAM(conv_integer(raddrB & conv_std_logic_vector(i,log2(R))));
|
<= RAM(conv_integer(raddr & conv_std_logic_vector(i,log2(R))));
|
end loop;
|
end loop;
|
end if;
|
end if;
|
end process;
|
end process;
|
end generate;
|
end generate;
|
|
|
altera_device : if device="altera" generate
|
altera_device : if device="altera" generate
|
-- Use a multidimensional array to model mixed-width
|
-- Use a multidimensional array to model mixed-width
|
type word_t is array(R-1 downto 0) of std_logic_vector(wrwidth-1 downto 0);
|
type word_t is array(R-1 downto 0) of std_logic_vector(wrwidth-1 downto 0);
|
type ram_t is array (0 to rddepth-1) of word_t;
|
type ram_t is array (0 to rddepth-1) of word_t;
|
|
|
shared variable ram : ram_t;
|
signal ram : ram_t;
|
signal q_local : word_t;
|
signal q_local : word_t;
|
-- altera constraints:
|
-- altera constraints:
|
-- for smal depths:
|
-- for smal depths:
|
-- if the synthesis option "allow any size of RAM to be inferred" is on, these lines
|
-- if the synthesis option "allow any size of RAM to be inferred" is on, these lines
|
-- may be left commented.
|
-- may be left commented.
|
-- uncomment this attribute if that option is off and you know wich primitives should be used.
|
-- uncomment this attribute if that option is off and you know wich primitives should be used.
|
--attribute ramstyle : string;
|
--attribute ramstyle : string;
|
--attribute ramstyle of RAM : signal is "M9K, no_rw_check";
|
--attribute ramstyle of RAM : signal is "M9K, no_rw_check";
|
begin
|
begin
|
unpack: for i in 0 to R - 1 generate
|
unpack: for i in 0 to R - 1 generate
|
doutB(wrwidth*(i+1) - 1 downto wrwidth*i) <= q_local(i);
|
dout(wrwidth*(i+1) - 1 downto wrwidth*i) <= q_local(i);
|
end generate unpack;
|
end generate unpack;
|
|
|
process(clkA)
|
process(clk, we)
|
begin
|
begin
|
if(rising_edge(clkA)) then
|
if(rising_edge(clk)) then
|
if(weA = '1') then
|
if(we = '1') then
|
ram(conv_integer(waddrA)/R)(conv_integer(waddrA) mod R) := dinA;
|
ram(conv_integer(waddr)/R)(conv_integer(waddr) mod R) <= din;
|
end if;
|
end if;
|
end if;
|
q_local <= ram(conv_integer(raddr));
|
end process;
|
|
|
|
process(clkB)
|
|
begin
|
|
if(rising_edge(clkB)) then
|
|
q_local <= ram(conv_integer(raddrB));
|
|
end if;
|
end if;
|
end process;
|
end process;
|
end generate;
|
end generate;
|
|
|
end behavorial;
|
end behavorial;
|
