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https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [dpram_generic.vhd] - Diff between revs 59 and 60
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| Rev 59 |
Rev 60 |
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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- behovorial description of a dual port ram with one 32-bit ----
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---- behavorial description of a dual port ram with one 32-bit ----
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---- write port and one 32-bit read port ----
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---- write port and one 32-bit read port ----
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---- ----
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---- ----
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---- Dependencies: none ----
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---- Dependencies: none ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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signal ram : ram_type;
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signal ram : ram_type;
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-- xilinx constraint to use blockram resources
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-- xilinx constraint to use blockram resources
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attribute ram_style : string;
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attribute ram_style : string;
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attribute ram_style of ram:signal is "block";
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attribute ram_style of ram:signal is "block";
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-- altera constraint
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-- altera constraints:
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attribute ramstyle : string;
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-- for smal depths:
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attribute ramstyle of ram : signal is "M9K, no_rw_check";
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-- if the synthesis option : allow any size of RAM to be inferred, is on these lines
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-- may be left uncommented.
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-- uncomment this attribute if that option is of and you know wich primitives should be used.
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--attribute ramstyle : string;
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--attribute ramstyle of ram : signal is "M9K, no_rw_check";
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begin
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begin
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process (clk)
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process (clk)
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begin
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begin
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if (clk'event and clk = '1') then
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if (clk'event and clk = '1') then
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if (we = '1') then
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if (we = '1') then
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