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entity dpram_generic is
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entity dpram_generic is
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generic (
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generic (
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depth : integer := 2
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depth : integer := 2
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);
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);
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port (
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port (
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clk : in std_logic;
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-- write port A
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-- write port
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clkA : in std_logic;
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waddr : in std_logic_vector(log2(depth)-1 downto 0);
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waddrA : in std_logic_vector(log2(depth)-1 downto 0);
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we : in std_logic;
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weA : in std_logic;
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din : in std_logic_vector(31 downto 0);
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dinA : in std_logic_vector(31 downto 0);
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-- read port
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-- read port B
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raddr : in std_logic_vector(log2(depth)-1 downto 0);
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clkB : in std_logic;
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dout : out std_logic_vector(31 downto 0)
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raddrB : in std_logic_vector(log2(depth)-1 downto 0);
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doutB : out std_logic_vector(31 downto 0)
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);
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);
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end dpram_generic;
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end dpram_generic;
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architecture behavorial of dpram_generic is
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architecture behavorial of dpram_generic is
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-- the memory
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-- the memory
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type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
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type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
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signal RAM : ram_type := (others => (others => '0'));
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shared variable RAM : ram_type := (others => (others => '0'));
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-- xilinx constraint to use blockram resources
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-- xilinx constraint to use blockram resources
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attribute ram_style : string;
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attribute ram_style : string;
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attribute ram_style of ram:signal is "block";
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attribute ram_style of ram:variable is "block";
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-- altera constraints:
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-- altera constraints:
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-- for smal depths:
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-- for smal depths:
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-- if the synthesis option "allow any size of RAM to be inferred" is on, these lines
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-- if the synthesis option "allow any size of RAM to be inferred" is on, these lines
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-- may be left commented.
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-- may be left commented.
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-- uncomment this attribute if that option is off and you know wich primitives should be used.
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-- uncomment this attribute if that option is off and you know wich primitives should be used.
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--attribute ramstyle : string;
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--attribute ramstyle : string;
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--attribute ramstyle of RAM : signal is "M9K, no_rw_check";
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--attribute ramstyle of RAM : variable is "M9K, no_rw_check";
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begin
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begin
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process (clk)
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process (clkA)
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begin
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begin
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if (clk'event and clk = '1') then
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if rising_edge(clkA) then
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if (we = '1') then
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if (weA = '1') then
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RAM(conv_integer(waddr)) <= din;
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RAM(conv_integer(waddrA)) := dinA;
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end if;
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end if;
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dout <= RAM(conv_integer(raddr));
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end if;
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end if;
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end process;
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end process;
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process (clkB)
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begin
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if rising_edge(clkB) then
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doutB <= RAM(conv_integer(raddrB));
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end if;
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end process;
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end behavorial;
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end behavorial;
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