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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [dpramblock_asym.vhd] - Diff between revs 90 and 94
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| Rev 90 |
Rev 94 |
| Line 60... |
Line 60... |
width : integer := 256; -- read width
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width : integer := 256; -- read width
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depth : integer := 2; -- nr of (width)-bit words
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depth : integer := 2; -- nr of (width)-bit words
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device : string := "xilinx"
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device : string := "xilinx"
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);
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);
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port (
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port (
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clk : in std_logic;
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-- write port A
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-- write port
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clkA : in std_logic;
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waddr : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
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waddrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
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we : in std_logic;
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weA : in std_logic;
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din : in std_logic_vector(31 downto 0);
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dinA : in std_logic_vector(31 downto 0);
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-- read port
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-- read port B
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raddr : in std_logic_vector(log2(depth)-1 downto 0);
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clkB : in std_logic;
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dout : out std_logic_vector(width-1 downto 0)
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raddrB : in std_logic_vector(log2(depth)-1 downto 0);
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doutB : out std_logic_vector(width-1 downto 0)
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);
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);
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end dpramblock_asym;
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end dpramblock_asym;
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architecture structural of dpramblock_asym is
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architecture structural of dpramblock_asym is
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-- constants
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-- constants
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| Line 90... |
Line 91... |
rddepth => depth,
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rddepth => depth,
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wrwidth => RAMwrwidth,
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wrwidth => RAMwrwidth,
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device => device
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device => device
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)
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)
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port map(
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port map(
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clk => clk,
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-- write port
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-- write port
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waddr => waddr,
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clkA => clkA,
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we => we,
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waddrA => waddrA,
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din => din((i+1)*RAMwrwidth-1 downto RAMwrwidth*i),
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weA => weA,
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dinA => dinA((i+1)*RAMwrwidth-1 downto RAMwrwidth*i),
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-- read port
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-- read port
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raddr => raddr,
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clkB => clkB,
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dout => dout_RAM(i)
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raddrB => raddrB,
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doutB => dout_RAM(i)
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);
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);
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map_output : for j in 0 to nrRAMs-1 generate
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map_output : for j in 0 to nrRAMs-1 generate
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dout(j*32+(i+1)*RAMwrwidth-1 downto j*32+i*RAMwrwidth)
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doutB(j*32+(i+1)*RAMwrwidth-1 downto j*32+i*RAMwrwidth)
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<= dout_RAM(i)((j+1)*RAMwrwidth-1 downto j*RAMwrwidth);
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<= dout_RAM(i)((j+1)*RAMwrwidth-1 downto j*RAMwrwidth);
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end generate;
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end generate;
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end generate;
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end generate;
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end structural;
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end structural;
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