| Line 60... |
Line 60... |
depthB : integer := 4; -- nr of 32-bit words
|
depthB : integer := 4; -- nr of 32-bit words
|
widthA : integer := 2; -- port A width, must be smaller than or equal to 32
|
widthA : integer := 2; -- port A width, must be smaller than or equal to 32
|
device : string := "xilinx"
|
device : string := "xilinx"
|
);
|
);
|
port (
|
port (
|
clk : in std_logic;
|
|
-- port A (widthA)-bit
|
-- port A (widthA)-bit
|
|
clkA : in std_logic;
|
addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0);
|
addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0);
|
weA : in std_logic;
|
weA : in std_logic;
|
dinA : in std_logic_vector(widthA-1 downto 0);
|
dinA : in std_logic_vector(widthA-1 downto 0);
|
doutA : out std_logic_vector(widthA-1 downto 0);
|
doutA : out std_logic_vector(widthA-1 downto 0);
|
-- port B 32-bit
|
-- port B 32-bit
|
|
clkB : in std_logic;
|
addrB : in std_logic_vector(log2(depthB)-1 downto 0);
|
addrB : in std_logic_vector(log2(depthB)-1 downto 0);
|
weB : in std_logic;
|
weB : in std_logic;
|
dinB : in std_logic_vector(31 downto 0);
|
dinB : in std_logic_vector(31 downto 0);
|
doutB : out std_logic_vector(31 downto 0)
|
doutB : out std_logic_vector(31 downto 0)
|
);
|
);
|
| Line 90... |
Line 91... |
-- You need to declare ram as a shared variable when :
|
-- You need to declare ram as a shared variable when :
|
-- - the RAM has two write ports,
|
-- - the RAM has two write ports,
|
-- - the RAM has only one write port whose data width is maxWIDTH
|
-- - the RAM has only one write port whose data width is maxWIDTH
|
-- In all other cases, ram can be a signal.
|
-- In all other cases, ram can be a signal.
|
shared variable ram : ramType := (others => (others => '0'));
|
shared variable ram : ramType := (others => (others => '0'));
|
signal clkA : std_logic;
|
|
signal clkB : std_logic;
|
|
|
|
begin
|
begin
|
clkA <= clk;
|
|
process (clkA)
|
process (clkA)
|
begin
|
begin
|
if rising_edge(clkA) then
|
if rising_edge(clkA) then
|
if weA = '1' then
|
if weA = '1' then
|
ram(conv_integer(addrA)) := dinA;
|
ram(conv_integer(addrA)) := dinA;
|
end if;
|
end if;
|
doutA <= ram(conv_integer(addrA));
|
doutA <= ram(conv_integer(addrA));
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
clkB <= clk;
|
|
process (clkB)
|
process (clkB)
|
begin
|
begin
|
if rising_edge(clkB) then
|
if rising_edge(clkB) then
|
for i in 0 to R-1 loop
|
for i in 0 to R-1 loop
|
if weB = '1' then
|
if weB = '1' then
|
| Line 147... |
Line 144... |
wB_local(i) <= dinB(widthA*(i+1)-1 downto widthA*i);
|
wB_local(i) <= dinB(widthA*(i+1)-1 downto widthA*i);
|
doutB(widthA*(i+1)-1 downto widthA*i) <= qB_local(i);
|
doutB(widthA*(i+1)-1 downto widthA*i) <= qB_local(i);
|
end generate unpack;
|
end generate unpack;
|
|
|
--port B
|
--port B
|
process(clk)
|
process(clkB)
|
begin
|
begin
|
if(rising_edge(clk)) then
|
if(rising_edge(clkB)) then
|
if(weB = '1') then
|
if(weB = '1') then
|
ram(conv_integer(addrB)) <= wB_local;
|
ram(conv_integer(addrB)) <= wB_local;
|
end if;
|
end if;
|
qB_local <= ram(conv_integer(addrB));
|
qB_local <= ram(conv_integer(addrB));
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- port A
|
-- port A
|
process(clk)
|
process(clkA)
|
begin
|
begin
|
if(rising_edge(clk)) then
|
if(rising_edge(clkA)) then
|
doutA <= ram(conv_integer(addrA) / R )(conv_integer(addrA) mod R);
|
doutA <= ram(conv_integer(addrA) / R )(conv_integer(addrA) mod R);
|
if(weA ='1') then
|
if(weA ='1') then
|
ram(conv_integer(addrA) / R)(conv_integer(addrA) mod R) <= dinA;
|
ram(conv_integer(addrA) / R)(conv_integer(addrA) mod R) <= dinA;
|
end if;
|
end if;
|
end if;
|
end if;
|
