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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [tdpramblock_asym.vhd] - Diff between revs 89 and 90
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| Rev 89 |
Rev 90 |
| Line 60... |
Line 60... |
depth : integer := 4; -- nr of (width)-bit words
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depth : integer := 4; -- nr of (width)-bit words
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width : integer := 512; -- width of portB
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width : integer := 512; -- width of portB
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device : string := "xilinx"
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device : string := "xilinx"
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);
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);
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port (
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port (
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clk : in std_logic;
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-- port A 32-bit
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-- port A 32-bit
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clkA : in std_logic;
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addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
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addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
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weA : in std_logic;
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weA : in std_logic;
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dinA : in std_logic_vector(31 downto 0);
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dinA : in std_logic_vector(31 downto 0);
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doutA : out std_logic_vector(31 downto 0);
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doutA : out std_logic_vector(31 downto 0);
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-- port B (width)-bit
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-- port B (width)-bit
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clkB : in std_logic;
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addrB : in std_logic_vector(log2(depth)-1 downto 0);
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addrB : in std_logic_vector(log2(depth)-1 downto 0);
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weB : in std_logic;
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weB : in std_logic;
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dinB : in std_logic_vector(width-1 downto 0);
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dinB : in std_logic_vector(width-1 downto 0);
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doutB : out std_logic_vector(width-1 downto 0)
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doutB : out std_logic_vector(width-1 downto 0)
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);
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);
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| Line 94... |
Line 93... |
widthA => RAMwidthA,
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widthA => RAMwidthA,
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depthB => depth,
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depthB => depth,
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device => device
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device => device
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)
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)
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port map(
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port map(
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clk => clk,
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-- port A (widthA)-bit
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-- port A (widthA)-bit
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clkA => clkA,
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addrA => addrA,
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addrA => addrA,
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weA => weA,
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weA => weA,
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dinA => dinA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
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dinA => dinA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
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doutA => doutA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
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doutA => doutA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
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-- port B 32-bit
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-- port B 32-bit
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clkB => clkB,
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addrB => addrB,
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addrB => addrB,
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weB => weB,
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weB => weB,
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dinB => dinB_RAM(i),
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dinB => dinB_RAM(i),
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doutB => doutB_RAM(i)
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doutB => doutB_RAM(i)
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);
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);
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