| Line 188... |
Line 188... |
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Read asignments
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-- Read asignments
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-- if reading registers, do ack, else use internal ack
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-- if reading registers, do ack, else use internal ack
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ACK_O_port <= CYC_I_port and STB_I_port and (not(ADR_I_port(3)) or ACK_I_int or not(running_I));
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ACK_O_port <= (CYC_I_port and STB_I_port) and
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((not(ADR_I_port(3)) or ACK_I_int or not(running_I)));
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Internal wishbone allocation
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-- Internal wishbone allocation
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STB_O_int <= STB_I_port and ADR_I_port(3);
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STB_O_int <= STB_I_port and ADR_I_port(3);
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| Line 223... |
Line 224... |
time_scale_R <= (others => '0');
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time_scale_R <= (others => '0');
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channels_sel_R <= (others => '0');
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channels_sel_R <= (others => '0');
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buffer_size_R <= (others => '0');
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buffer_size_R <= (others => '0');
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trigger_level_R <= (others => '0');
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trigger_level_R <= (others => '0');
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trigger_offset_R <= (others => '0');
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trigger_offset_R <= (others => '0');
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trigger_channel_R <= (others => '0');
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write_in_adc_R <= '0';
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adc_conf_R <= (others => '0');
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-- Assignments
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-- Assignments
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elsif CYC_I_port = '1' and STB_I_port = '1' and WE_I_port = '1' and ADR_I_port(3) = '0' then
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elsif CYC_I_port = '1' and STB_I_port = '1' and WE_I_port = '1' and ADR_I_port(3) = '0' then
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case ADR_I_port(2 downto 0) is
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case ADR_I_port(2 downto 0) is
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