| Line 12... |
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--|
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--|
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--|
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--|
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.1 | jul-2009 | First testing
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--| 0.1 | jul-2009 | First testing
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--| 0.2 | aug-2009 | New status flag
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright © 2009, Facundo Aguilera.
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--| Copyright © 2009, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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| Line 49... |
Line 50... |
-- TrOff07|TrOff06|TrOff00|TrOff00|TrOff00|TrOff00|TrOff00|TrOff00]
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-- TrOff07|TrOff06|TrOff00|TrOff00|TrOff00|TrOff00|TrOff00|TrOff00]
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--
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--
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-- 05 ADCConf RW [ | | | | ADCS|ADSleep| ADPSEn| ADPS08|
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-- 05 ADCConf RW [ | | | | ADCS|ADSleep| ADPSEn| ADPS08|
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-- ADPS07| ADPS06| ADPS05| ADPS04| ADPS03| ADPS02| ADPS01| ADPS00]
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-- ADPS07| ADPS06| ADPS05| ADPS04| ADPS03| ADPS02| ADPS01| ADPS00]
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--
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--
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-- 08 Data_O R [ErrFlag|RunFlag| | | | DCh00| Dat09| Dat08|
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-- 08 Data_O R [StatF01|StatF00| | | | DCh00| Dat09| Dat08|
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-- Dat07| Dat06| Dat05| Dat04| Dat03| Dat02| Dat01| Dat00]
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-- Dat07| Dat06| Dat05| Dat04| Dat03| Dat02| Dat01| Dat00]
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--
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--
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-- 09 Error_O R [ | | | | | | | |
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-- 09 Error_O R [ | | | | | | | |
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-- | | | | | ErrN02| ErrN01| ErrN00]
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-- | | | | | ErrN02| ErrN01| ErrN00]
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--
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--
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--
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--
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--
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--
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-- Description
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-- Description
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--
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-- StatF01|StatF00|
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-- 00 Stoped
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-- 01 Running, odd buffer
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-- 11 Running, pair buffer
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-- 10 Stoped, with error
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--==================================================================================================
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--==================================================================================================
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library ieee;
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library ieee;
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Line 124... |
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adc_conf_O: out std_logic_vector(15 downto 0);
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adc_conf_O: out std_logic_vector(15 downto 0);
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error_number_I: in std_logic_vector (2 downto 0);
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error_number_I: in std_logic_vector (2 downto 0);
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--data_channel_I: in std_logic;
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--data_channel_I: in std_logic;
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running_I: in std_logic;
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status_I: in std_logic_vector(1 downto 0);
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error_flag_I: in std_logic;
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write_in_adc_O: out std_logic;
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write_in_adc_O: out std_logic;
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stop_O: out std_logic
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stop_O: out std_logic
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-- Stop the current conversion when reading
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-- Stop the current conversion when reading
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);
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);
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Line 183... |
o_selector(5) <= adc_conf_R;
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o_selector(5) <= adc_conf_R;
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o_selector(6) <= (others => '0');
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o_selector(6) <= (others => '0');
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o_selector(7) <= (others => '0');
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o_selector(7) <= (others => '0');
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o_selector(8) <= error_flag_I & running_I & (13 downto 11 => '0') & data_channel & data;
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o_selector(8) <= status_I & (13 downto 11 => '0') & data_channel & data;
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o_selector(9) <= (15 downto 3 => '0') & error_number_I;
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o_selector(9) <= (15 downto 3 => '0') & error_number_I;
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DAT_O_port <= o_selector(conv_integer(ADR_I_port));
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DAT_O_port <= o_selector(conv_integer(ADR_I_port));
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Read asignments
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-- Read asignments
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-- if reading registers, do ack, else use internal ack
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-- if reading registers, do ack, else use internal ack
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ACK_O_port <= (CYC_I_port and STB_I_port) and
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ACK_O_port <= (CYC_I_port and STB_I_port) and
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((not(ADR_I_port(3)) or ACK_I_int or not(running_I)));
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((not(ADR_I_port(3)) or ACK_I_int or not(status_I(0))));
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Internal wishbone allocation
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-- Internal wishbone allocation
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STB_O_int <= STB_I_port and ADR_I_port(3);
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STB_O_int <= STB_I_port and ADR_I_port(3);
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