| Line 1... |
Line 1... |
-------------------------------------------------------------------------------------------------100
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-------------------------------------------------------------------------------------------------100
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: ctrl_address_allocation.vhd
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--| File: ctrl_address_allocation.vhd
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--| Version: 0.1
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--| Version: 0.21
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--| Tested in: Actel A3PE1500
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--| Tested in: Actel A3PE1500
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| CONTROL - Address allocations
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--| CONTROL - Address allocations
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--|
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--| Registers and intercomunications.
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--|
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--|
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.1 | jul-2009 | First testing
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--| 0.1 | jul-2009 | First testing
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--| 0.2 | aug-2009 | New status flag
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--| 0.2 | aug-2009 | New status flag
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--| 0.21 | sep-2009 | Smarter stop signal
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright © 2009, Facundo Aguilera.
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--| Copyright © 2009, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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|
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--| Wishbone Rev. B.3 compatible
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--==================================================================================================
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--==================================================================================================
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-- TO DO
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-- TO DO
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-- · Finish ADC conf write
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-- [OK] Finish ADC conf write
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-- · Define error codes
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--==================================================================================================
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--==================================================================================================
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--==================================================================================================
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--==================================================================================================
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-- Allocations
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-- Allocations
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| Line 203... |
Line 208... |
STB_O_int <= STB_I_port and ADR_I_port(3);
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STB_O_int <= STB_I_port and ADR_I_port(3);
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CYC_O_int <= CYC_I_port and ADR_I_port(3);
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CYC_O_int <= CYC_I_port and ADR_I_port(3);
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|
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Stop signal
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-- Stop signal
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stop_O <= CYC_I_port and STB_I_port and WE_I_port;
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-- It asserts when there is a write in the confing registers
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P_stop: process (CLK_I, STB_I_port, WE_I_port, status_I, ADR_I_port)
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begin
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if CLK_I'event and CLK_I = '1' then
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if status_I(0) = '0' then
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stop_O <= '0';
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elsif CYC_I_port = '1' and STB_I_port = '1' and WE_I_port = '1' and ADR_I_port(3) = '0' then
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stop_O <= '1';
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end if;
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end if;
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end process;
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- DAT_I
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-- DAT_I
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data <= DAT_I_int(9 downto 0);
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data <= DAT_I_int(9 downto 0);
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data_channel <= DAT_I_int(10);
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data_channel <= DAT_I_int(10);
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