| Line 1... |
Line 1... |
-------------------------------------------------------------------------------------------------100
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-------------------------------------------------------------------------------------------------100
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: ctrl_channel_selector.vhd
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--| File: ctrl_channel_selector.vhd
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--| Version: 0.3
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--| Version: 0.31
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--| Tested in: Actel A3PE1500
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--| Tested in: Actel A3PE1500
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| CONTROL - Channel Selector
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--| CONTROL - Channel Selector
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| Line 14... |
Line 14... |
--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.1 | jul-2009 | First testing
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--| 0.1 | jul-2009 | First testing
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--| 0.2 | jul-2009 | Added generic number of channel
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--| 0.2 | jul-2009 | Added generic number of channel
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--| 0.3 | jul-2009 | Added signal indicating when it's selecting the first channel
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--| 0.3 | jul-2009 | Added signal indicating when it's selecting the first channel
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--| 0.31 | aug-2009 | Generic width in channel_number
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright © 2009, Facundo Aguilera.
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--| Copyright © 2009, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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| Line 25... |
Line 26... |
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--==================================================================================================
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--==================================================================================================
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-- TODO
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-- TODO
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-- · Speed up...
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-- · Speed up...
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-- · Generic width in channel_number_O
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-- OK Generic width in channel_number_O
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--==================================================================================================
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--==================================================================================================
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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| Line 44... |
Line 45... |
generic(
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generic(
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CHANNEL_WIDTH: integer := 4 -- number of channels 2**CHANNEL_WIDTH, max. 4
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CHANNEL_WIDTH: integer := 4 -- number of channels 2**CHANNEL_WIDTH, max. 4
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);
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);
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port(
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port(
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channels_I: in std_logic_vector(integer(2**real(CHANNEL_WIDTH))-1 downto 0);
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channels_I: in std_logic_vector(integer(2**real(CHANNEL_WIDTH))-1 downto 0);
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channel_number_O: out std_logic_vector(3 downto 0);
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channel_number_O: out std_logic_vector(CHANNEL_WIDTH-1 downto 0);
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first_channel_O: out std_logic;
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first_channel_O: out std_logic;
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clk_I: in std_logic;
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clk_I: in std_logic;
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enable_I: in std_logic;
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enable_I: in std_logic;
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reset_I: in std_logic
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reset_I: in std_logic
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);
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);
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end entity channel_selector;
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end entity ctrl_channel_selector;
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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architecture ARCH01 of ctrl_channel_selector is
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architecture ARCH01 of ctrl_channel_selector is
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| Line 69... |
Line 70... |
signal plus: unsigned(CHANNEL_WIDTH downto 0);
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signal plus: unsigned(CHANNEL_WIDTH downto 0);
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begin
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begin
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|
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Output
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-- Output
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channel_number_O <= (3 downto CHANNEL_WIDTH => '0') & std_logic_vector(channel);
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channel_number_O <= std_logic_vector(channel);
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--channel_number_O <= std_logic_vector(channel);
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--channel_number_O <= std_logic_vector(channel);
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Combinational selection of next channel
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-- Combinational selection of next channel
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|
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-- P_comb: process(channel,channels_I)
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-- P_comb: process(channel,channels_I)
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