Subversion Repositories modular_oscilloscope

-------------------------------------------------------------------------------------------------100

--| Modular Oscilloscope

--| UNSL - Argentine

--|

--| File: ctrl.vhd

--| Version: 0.1

--| Tested in: Actel A3PE1500

--|   Board: RVI Prototype Board + LP Data Conversion Daughter Board

--|-------------------------------------------------------------------------------------------------

--| Description:

--|   CONTROL - Control system

--|   This is the tom modules in the folder.

--|   

--|-------------------------------------------------------------------------------------------------

--| File history:

--|   0.1   | aug-2009 | First testing

----------------------------------------------------------------------------------------------------

--| Copyright © 2009, Facundo Aguilera.

--|

--| This VHDL design file is an open design; you can redistribute it and/or

--| modify it and/or implement it after contacting the author.

----------------------------------------------------------------------------------------------------

--==================================================================================================

-- TO DO

-- · ...

--==================================================================================================

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.math_real.all;

use work.ctrl_pkg.all;

entity ctrl is

  port(

    ------------------------------------------------------------------------------------------------

    -- From port

    DAT_I_port: in  std_logic_vector (15 downto 0);

    DAT_O_port: out std_logic_vector (15 downto 0);

    ADR_I_port: in  std_logic_vector (3 downto 0);

    CYC_I_port: in  std_logic;

    STB_I_port: in  std_logic;

    ACK_O_port: out std_logic ;

    WE_I_port:  in  std_logic;

    CLK_I_port: in std_logic;

    RST_I_port: in std_logic;

    ------------------------------------------------------------------------------------------------

    -- To ADC

    DAT_I_daq: in  std_logic_vector (15 downto 0);

    DAT_O_daq: out std_logic_vector (15 downto 0);

    ADR_O_daq: out std_logic_vector (3 downto 0);

    CYC_O_daq: out std_logic;

    STB_O_daq: out std_logic;

    ACK_I_daq: in  std_logic ;

    WE_O_daq:  out std_logic;

    CLK_I_daq: in std_logic;

    RST_I_daq: in std_logic;

    ------------------------------------------------------------------------------------------------

    -- To memory, A (writing) interface (Higer prioriry)

    --DAT_I_memw: in  std_logic_vector (15 downto 0);

    DAT_O_memw: out std_logic_vector (15 downto 0);

    ADR_O_memw: out  std_logic_vector (13 downto 0);

    CYC_O_memw: out  std_logic;

    STB_O_memw: out  std_logic;

    ACK_I_memw: in std_logic ;

    WE_O_memw:  out  std_logic;

    ------------------------------------------------------------------------------------------------

    -- To memory, B (reading) interface

    DAT_I_memr: in  std_logic_vector (15 downto 0);

    --DAT_O_memr: out std_logic_vector (15 downto 0);

    ADR_O_memr: out  std_logic_vector (13 downto 0);

    CYC_O_memr: out  std_logic;

    STB_O_memr: out  std_logic;

    ACK_I_memr: in std_logic ;

    WE_O_memr:  out  std_logic

  );

end entity ctrl;

architecture WSM of ctrl is

  type StateType is (

          ST_IDLE,

          ST_INIT,

          ST_RUNNING

          );

  signal next_state, present_state: StateType;

  --------------------------------------------------------------------------------------------------

  -- Interconnections

  -- internal wb

  signal cyc_to_outmgr:       std_logic;

  signal stb_to_outmgr:       std_logic;

  signal ack_from_outmgr:     std_logic;

  signal dat_from_outmgr:     std_logic_vector(15 downto 0);

  -- trigger

  signal trigger_reset:           std_logic;

  signal trigger_en:              std_logic;

  signal trigger_out_adr:             std_logic;

  signal reg_trigger_en:          std_logic;

  signal reg_trigger_edge:        std_logic;

  signal reg_trigger_level:       std_logic_vector(9 downto 0);

  signal reg_trigger_offset:      std_logic_vector(14 downto 0);

  signal reg_trigger_channel:     std_logic;

  -- channels

  signal reg_channels_selection:  std_logic_vector(1 downto 0);

  signal chsel_first_channel:     std_logic;

  signal chsel_channel:           std_logic_vector(3 downto 0);

  signal chsel_reset:             std_logic;

  signal chsel_en:                std_logic;

  -- address

  signal buffer_size:         std_logic_vector(13 downto 0);

  -- skipper

  signal dskip_en:         std_logic;

  signal dskip_reset:      std_logic;

  signal dskip_out_ack:      std_logic;

  signal dskip_in_stb:      std_logic;

  -- Memory writer

  signal memwr_en:          std_logic;

  signal memwr_reset:       std_logic;

  signal memwr_stb:         std_logic;

  signal memwr_ack:         std_logic;

  signal memwr_continuous:  std_logic;

  signal memwr_out_adr:     std_logic_vector (14 downto 0);

  signal memwr_in_dat:      std_logic_vector (15 downto 0);

  -- outmgr

  signal outmgr_reset:        std_logic;

  signal outmgr_en:           std_logic;

  signal outmgr_load:         std_logic;

  signal outmgr_initial_adr:  std_logic;

  --signal outmgr_pause_adr:    std_logic; -- ??

  signal outmgr_finish:       std_logic;

  signal time_scale:          std_logic_vector(4 downto 0);

  signal time_scale_en:       std_logic;

  --------------------------------------------------------------------------------------------------

  -- Flags

  signal running: std_logic;

  signal stop: std_logic;

  signal start: std_logic;

  signal continuous: std_logic;

begin

  --------------------------------------------------------------------------------------------------

  -- Instances

  U_OUTMGR0: ctrl_output_manager

  generic map(

      MEM_ADD_WIDTH => 14 --: integer :=  14

    )

    port map(

      ----------------------------------------------------------------------------------------------

      -- MASTER (to memory) 

      DAT_I_mem => DAT_I_memr, -- direct

      ADR_O_mem => ADR_O_memr, -- direct

      CYC_O_mem => CYC_O_memr, -- direct

      STB_O_mem => STB_O_memr, -- direct

      ACK_I_mem => ACK_I_memr, -- direct

      WE_O_mem  => WE_O_memr, -- direct

      ----------------------------------------------------------------------------------------------

      -- SLAVE (to I/O ports) 

      DAT_O_port => dat_from_outmgr,

      CYC_I_port => cyc_to_outmgr,

      STB_I_port => stb_to_outmgr,

      ACK_O_port => ack_from_outmgr,

      WE_I_port  => '0',

      ------------------------------------------------------------------------------------------------

      -- Common signals 

      RST_I      => RST_I_port, -- direct

      CLK_I      => CLK_I_port, -- direct

      ------------------------------------------------------------------------------------------------

      -- Internal

      load_I            => outmgr_load,

      enable_I          => outmgr_en,

      initial_address_I => outmgr_initial_adr,

      biggest_address_I => buffer_size,

      pause_address_I   => memwr_out_adr, -- define

      finish_O          => outmgr_finish

    );

  U_CTRL_MEMWR0: ctrl_memory_writer

    generic map(

      MEM_ADD_WIDTH => 14--: integer :=  14

    )

    port map(

      -- to memory

      DAT_O_mem => DAT_O_memw, -- direct

      ADR_O_mem => memwr_out_adr,   --!

      CYC_O_mem => CYC_O_memw, -- direct

      STB_O_mem => STB_O_memw, -- direct

      ACK_I_mem => ACK_I_memw, -- direct

      WE_O_mem  => WE_O_memw, -- direct

      -- to acquistion module

      DAT_I_adc => memwr_in_dat,    --!

      CYC_O_adc => CYC_O_adc, -- direct

      STB_O_adc => memwr_stb,

      ACK_I_adc => memwr_ack,

      WE_O_adc  => WE_O_adc, -- direct

      -- Common signals 

      RST_I => RST_I_daq, -- direct

      CLK_I => CLK_I_daq, -- direct

      -- Internal

      reset_I         => memwr_reset,

      enable_I        => memwr_en,

      final_address_I => buffer_size,

      finished_O      => memwr_finish,

      continuous_I    => memwr_continuous

    );

  U_CTRL_DSKIP0: ctrl_data_skipper

    generic map(

      SELECTOR_WIDTH    => 5,--: integer := 5 

    )

    port map(

      ack_O             => dskip_out_ack,

      ack_I             => ACK_I_daq,

      stb_I             => dskip_in_stb,

      selector_I        => reg_time_scale,

      enable_skipper_I  => reg_time_scale_en,

      reset_I           => RST_I_daq,

      clk_I             => CLK_I_daq,

      first_channel_I   => chsel_first_channel

    );

  U_CTRL_CHSEL0: ctrl_channel_selector

    generic map(

      CHANNEL_WIDTH     => 4 --: integer := 4 -- number of channels 2**CHANNEL_WIDTH, max. 4

    )

    port map(

      channels_I        => reg_channels_selection,

      channel_number_O  => chsel_channel,

      first_channel_O   => chsel_first_channel,

      clk_I             => CLK_I_daq,

      enable_I          => chsel_en,

      reset_I           => chsel_reset

    );

  U_CTRL_TRIGGER0: ctrl_trigger_manager

    generic map(

      MEM_ADD_WIDTH   => 14,--:  integer := 14;

      DATA_WIDTH      => 10,--:     integer := 10;

      CHANNELS_WIDTH  => 1--: integer := 4

    )

    port map(

      data_I          => DAT_I_daq,

      channel_I       => chsel_channel,

      trig_channel_I  => reg_trigger_channel,

      address_I       => memwr_out_adr,

      final_address_I => reg_buffer_size,

      offset_I        => reg_trigger_offset,

      level_I         => reg_trigger_level,

      falling_I       => reg_trigger_edge,

      clk_I           => CLK_I_daq,

      reset_I         => trigger_reset,

      enable_I        => trigger_en,

      trigger_O       => trigger_act,

      address_O       => trigger_out_adr

    );

  -- reg_: signals from conf registers

  U_CTRL_ADDASSMNT0: ctrl_address_assignments

    port map(

      -- From port

      DAT_I_port        => DAT_I_port,

      DAT_O_port        => DAT_O_port,

      ADR_I_port        => ADR_I_port,

      CYC_I_port        => CYC_I_port,

      STB_I_port        => STB_I_port,

      ACK_O_port        => ACK_O_port,

      WE_I_port         => WE_I_port,

      RST_I             => RST_I_port,

      CLK_I             => CLK_I_port,

      -- To internal 

      CYC_O_int         => cyc_to_outmgr,

      STB_O_int         => stb_to_outmgr,

      ACK_I_int         => ack_from_outmgr,

      DAT_I_int         => dat_from_outmgr,

      -- Internal          

      time_scale_O      => reg_time_scale,

      time_scale_en_O   => reg_time_scale_en,

      channels_sel_O    => reg_channels_selection,

      buffer_size_O     => reg_buffer_size,

      trigger_en_O      => reg_trigger_en,

      trigger_edge_O    => reg_trigger_edge,

      trigger_level_O   => reg_trigger_level,

      trigger_offset_O  => reg_trigger_offset,

      trigger_channel_O => reg_trigger_channel,

      error_number_I    => "0000", -- not implemented yet

      data_channel_I    => data_channel_r,

      error_flag_I      => '0',   -- not implemented yet

      start_O           => start,

      continuous_O      => continuous,

      running_I         => running,

      stop_O            => stop

    );

  ------------------------------------------------------------------------------------------------

  -- Machine

  P_sm_comb: process ()

  begin

    case present_state is

      when ST_INIT =>

        memwr_reset       <= '1';

        memwr_en          <= '0';

        memwr_continuous  <= '-';

        dskip_reset   <= '1';

        dskip_en      <= '0';

        chsel_reset   <= '1';

        chsel_en      <= '0';

        trigger_reset <= '1';

        trigger_en    <= '0';

        next_state    <= ST_RUNNING;

      when ST_RUNNING =>

        memwr_reset       <= '0';

        memwr_en          <= ;

        memwr_continuous  <= ;

        dskip_reset   <= '0';

        dskip_en      <= reg_time_scale_en;

        chsel_reset   <= '0';

        chsel_en      <= dskip_out_ack;

        trigger_reset <= '0';

        trigger_en    <= reg_trigger_en and memwr_ack;

      when others =>  --ST_IDLE

    end case;

  end process;

  P_sm_clkd: process ()

  begin

    if RST_I_daq = '1' or stop = '1' then

      present_state <= ST_IDLE;

    elsif start = '1' then

      present_state <= ST_INIT;

    elsif CLK_I_daq'ecent and clk_I = '1' then

      present_state <= next_state;

    end if;

  end process;

  ------------------------------------------------------------------------------------------------

  -- Output

  P_OUTMGR: process (RST_I_port, stop, CLK_I_port, CLK_I_port, present_state, trigger_act,

  reg_trigger_en, memwr_out_adr, outmgr_en)

    if RST_I_port = '1' or present_state = IDLE or present_state = INIT then

      outmgr_load <= '0';

      outmgr_en   <=  '0';

    elsif CLK_I_port'event and CLK_I_port = '1' then

      if present_state = ST_RUNNING and trigger_act = '1' or (reg_trigger_en = '0' and

      memwr_out_adr != conv_integer(0) ) then

        outmgr_load <=  '1';

        outmgr_en   <=  '1';

        -- load must be set only one cycle

      elsif outmgr_en = '1' then

        load <= '0';

      end if;

    end if;

  end process;

  outmgr_initial_adr <= trigger_out_adr     when reg_trigger_en = '1' else

                        (others => '0');

end architecture;