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[/] [modular_oscilloscope/] [trunk/] [hdl/] [ctrl/] [ctrl.vhd] - Diff between revs 38 and 48

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Rev 38 Rev 48
Line 13... Line 13... 
--|   
--|   
--|-------------------------------------------------------------------------------------------------
 
--|-------------------------------------------------------------------------------------------------
 
--| File history:
 
--| File history:
 
--|   0.1   | aug-2009 | First testing
 
--|   0.1   | aug-2009 | First testing
 
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
 
--| Copyright © 2009, Facundo Aguilera.
 
--| Copyright © 2009, Facundo Aguilera (budinero at gmail.com).
 
--|
 
--|
 
--| This VHDL design file is an open design; you can redistribute it and/or
 
--| This VHDL design file is an open design; you can redistribute it and/or
 
--| modify it and/or implement it after contacting the author.
 
--| modify it and/or implement it after contacting the author.
 
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
 
 
 
 
 
 
 
 
 
--==================================================================================================
 
--==================================================================================================
 
-- TO DO
 
-- TO DO
 
-- · ...
 
-- · clean
 
--==================================================================================================
 
--==================================================================================================
 
library IEEE;
 
library IEEE;
 
use IEEE.STD_LOGIC_1164.ALL;
 
use IEEE.STD_LOGIC_1164.ALL;
 
 
 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
use ieee.math_real.all;
 
use ieee.math_real.all;
 
 
 
 
 
use work.ctrl_pkg.all;
 
use work.ctrl_pkg.all;
 
 
 
 
 
entity ctrl is
 
entity ctrl is
Line 48... Line 49... 
 
 
 
 
    ------------------------------------------------------------------------------------------------
 
    ------------------------------------------------------------------------------------------------
 
    -- To ADC
 
    -- To ADC
 
    DAT_I_daq: in  std_logic_vector (15 downto 0);
 
    DAT_I_daq: in  std_logic_vector (15 downto 0);
 
    DAT_O_daq: out std_logic_vector (15 downto 0);
 
    DAT_O_daq: out std_logic_vector (15 downto 0);
 
    ADR_O_daq: out std_logic_vector (3 downto 0);
 
    ADR_O_daq: out std_logic_vector (1 downto 0);
 
    CYC_O_daq: out std_logic;
 
    CYC_O_daq: out std_logic;
 
    STB_O_daq: out std_logic;
 
    STB_O_daq: out std_logic;
 
    ACK_I_daq: in  std_logic ;
 
    ACK_I_daq: in  std_logic ;
 
    WE_O_daq:  out std_logic;
 
    WE_O_daq:  out std_logic;
 
 
 
 
Line 83... Line 84... 
end entity ctrl;
 
end entity ctrl;
 
 
 
 
 
 
 
 
 
 
 
 
 
architecture WSM of ctrl is
 
architecture WSM of ctrl is
 
 
 
  -- machine
 
  type StateType is (
 
  type StateType is (
 
          ST_IDLE,
 
          ST_IDLE,
 
          ST_INIT,
 
          ST_INIT,
 
          ST_RUNNING
 
          ST_RUNNING,
 
 
 
          ST_ADCWRITE_INIT,
 
 
 
          ST_ADCWRITE
 
          );
 
          );
 
  signal next_state, present_state: StateType;
 
  signal next_state, present_state: StateType;
 
 
 
 
 
  --------------------------------------------------------------------------------------------------
 
 
 
  -- Interconnections
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  -- internal wb
 
 
 
  signal cyc_to_outmgr:       std_logic;
 
 
 
  signal stb_to_outmgr:       std_logic;
 
 
 
  signal ack_from_outmgr:     std_logic;
 
 
 
  signal dat_from_outmgr:     std_logic_vector(15 downto 0);
 
 
 
 
 
 
 
  -- trigger
 
  -- trigger
 
  signal trigger_reset:           std_logic;
 
  signal trigger_reset:           std_logic;
 
  signal trigger_en:              std_logic;
 
  signal trigger_en:              std_logic;
 
  signal trigger_out_adr:             std_logic;
 
  signal trigger_out_adr:         std_logic_vector(13 downto 0);
 
 
 
  signal trigger_act:              std_logic;
 
  signal reg_trigger_en:          std_logic;
 
  signal reg_trigger_en:          std_logic;
 
  signal reg_trigger_edge:        std_logic;
 
  signal reg_trigger_edge:        std_logic;
 
  signal reg_trigger_level:       std_logic_vector(9 downto 0);
 
  signal reg_trigger_level:       std_logic_vector(9 downto 0);
 
  signal reg_trigger_offset:      std_logic_vector(14 downto 0);
 
  signal reg_trigger_offset:      std_logic_vector(14 downto 0);
 
  signal reg_trigger_channel:     std_logic;
 
  signal reg_trigger_channel:     std_logic_vector(0 downto 0);
 
 
 
 
 
  -- channels
 
  -- channels
 
  signal reg_channels_selection:  std_logic_vector(1 downto 0);
 
  signal reg_channels_selection:  std_logic_vector(1 downto 0);
 
  signal chsel_first_channel:     std_logic;
 
  signal chsel_first_channel:     std_logic;
 
  signal chsel_channel:           std_logic_vector(3 downto 0);
 
  signal chsel_channel:           std_logic_vector(0 downto 0);
 
  signal chsel_reset:             std_logic;
 
  signal chsel_reset:             std_logic;
 
  signal chsel_en:                std_logic;
 
  --signal chsel_en:                std_logic;
 
 
 
 
 
  -- address
 
  -- address
 
  signal buffer_size:         std_logic_vector(13 downto 0);
 
  signal reg_buffer_size:         std_logic_vector(13 downto 0);
 
 
 
 
 
  -- skipper
 
  -- skipper
 
  signal dskip_en:         std_logic;
 
  --signal dskip_en:         std_logic;
 
  signal dskip_reset:      std_logic;
 
  signal dskip_reset:      std_logic;
 
  signal dskip_out_ack:      std_logic;
 
  signal dskip_out_ack:      std_logic;
 
  signal dskip_in_stb:      std_logic;
 
  signal reg_time_scale:     std_logic_vector(4 downto 0);
 
 
 
  signal reg_time_scale_en:  std_logic;
 
 
 
 
 
  -- Memory writer
 
  -- Memory writer
 
  signal memwr_en:          std_logic;
 
  signal memwr_en:          std_logic;
 
  signal memwr_reset:       std_logic;
 
  signal memwr_reset:       std_logic;
 
  signal memwr_stb:         std_logic;
 
  --signal memwr_ack:         std_logic;
 
  signal memwr_ack:         std_logic;
 
  --signal memwr_continuous:  std_logic;
 
  signal memwr_continuous:  std_logic;
 
  signal memwr_out_stb_daq: std_logic;
 
  signal memwr_out_adr:     std_logic_vector (14 downto 0);
 
  signal memwr_in_ack_mem:  std_logic;
 
 
 
  signal memwr_out_cyc_daq:  std_logic;
 
 
 
  signal memwr_out_adr:     std_logic_vector (13 downto 0);
 
  signal memwr_in_dat:      std_logic_vector (15 downto 0);
 
  signal memwr_in_dat:      std_logic_vector (15 downto 0);
 
 
 
 
 
  -- outmgr
 
  -- Outmgr
 
  signal outmgr_reset:        std_logic;
 
  --signal outmgr_reset:       std_logic;
 
  signal outmgr_en:           std_logic;
 
  signal outmgr_en:           std_logic;
 
  signal outmgr_load:         std_logic;
 
  signal outmgr_load:         std_logic;
 
  signal outmgr_initial_adr:  std_logic;
 
  signal outmgr_initial_adr: std_logic_vector(13 downto 0);
 
  --signal outmgr_pause_adr:    std_logic; -- ??
 
  --signal outmgr_pause_adr:    std_logic; -- ??
 
  signal outmgr_finish:       std_logic;
 
  signal outmgr_finish:       std_logic;
 
 
 
  signal outmgr_in_cyc:      std_logic;
 
 
 
  signal outmgr_in_stb:      std_logic;
 
 
 
  signal outmgr_out_akc:     std_logic;
 
 
 
  signal outmgr_out_dat:     std_logic_vector(15 downto 0);
 
 
 
 
 
 
 
  --------------------------------------------------------------------------------------------------
 
  signal time_scale:          std_logic_vector(4 downto 0);
 
  -- DAQ config
 
  signal time_scale_en:       std_logic;
 
  signal dat_to_adc: std_logic_vector(15 downto 0);
 
 
 
  signal strobe_adc: std_logic;
 
 
 
  signal write_in_adc: std_logic;
 
 
 
 
 
 
 
 
 
  --------------------------------------------------------------------------------------------------
 
  --------------------------------------------------------------------------------------------------
 
  -- Flags
 
  -- Flags
 
  signal running: std_logic;
 
  signal running: std_logic;
Line 166... Line 163... 
  signal continuous: std_logic;
 
  signal continuous: std_logic;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
begin
 
begin
 
  --------------------------------------------------------------------------------------------------
 
  --------------------------------------------------------------------------------------------------
 
  -- Instances
 
  -- Instances
 
 
 
 
 
  U_OUTMGR0: ctrl_output_manager
 
  U_OUTMGR0: ctrl_output_manager
 
  generic map(
 
  generic map(
 
      MEM_ADD_WIDTH => 14 --: integer :=  14
 
      MEM_ADD_WIDTH => 14 --: integer :=  14
 
    )
 
    )
 
    port map(
 
    port map(
 
      ----------------------------------------------------------------------------------------------
 
 
 
      -- MASTER (to memory) 
      -- MASTER (to memory) 
      DAT_I_mem => DAT_I_memr, -- direct
 
      DAT_I_mem => DAT_I_memr, -- direct
 
      ADR_O_mem => ADR_O_memr, -- direct
 
      ADR_O_mem => ADR_O_memr, -- direct
 
      CYC_O_mem => CYC_O_memr, -- direct
 
      CYC_O_mem => CYC_O_memr, -- direct
 
      STB_O_mem => STB_O_memr, -- direct
 
      STB_O_mem => STB_O_memr, -- direct
 
      ACK_I_mem => ACK_I_memr, -- direct
 
      ACK_I_mem => ACK_I_memr, -- direct
 
      WE_O_mem  => WE_O_memr, -- direct
 
      WE_O_mem  => WE_O_memr, -- direct
 
      ----------------------------------------------------------------------------------------------
 
 
 
      -- SLAVE (to I/O ports) 
      -- SLAVE (to I/O ports) 
      DAT_O_port => dat_from_outmgr,
 
      DAT_O_port => outmgr_out_dat,
 
      CYC_I_port => cyc_to_outmgr,
 
      CYC_I_port => outmgr_in_cyc,
 
      STB_I_port => stb_to_outmgr,
 
      STB_I_port => outmgr_in_stb,
 
      ACK_O_port => ack_from_outmgr,
 
      ACK_O_port => outmgr_out_akc,
 
      WE_I_port  => '0',
 
      WE_I_port  => '0',
 
      ------------------------------------------------------------------------------------------------
 
 
 
      -- Common signals 
      -- Common signals 
      RST_I      => RST_I_port, -- direct
 
      RST_I      => RST_I_port, -- direct
 
      CLK_I      => CLK_I_port, -- direct
 
      CLK_I      => CLK_I_port, -- direct
 
      ------------------------------------------------------------------------------------------------
 
 
 
      -- Internal
 
      -- Internal
 
      load_I            => outmgr_load,
 
      load_I            => outmgr_load,
 
      enable_I          => outmgr_en,
 
      enable_I          => outmgr_en,
 
      initial_address_I => outmgr_initial_adr,
 
      initial_address_I => outmgr_initial_adr,
 
      biggest_address_I => buffer_size,
 
      biggest_address_I => reg_buffer_size,
 
      pause_address_I   => memwr_out_adr, -- define
 
      pause_address_I   => memwr_out_adr,
 
      finish_O          => outmgr_finish
 
      finish_O          => outmgr_finish
 
    );
 
    );
 
 
 
 
 
  U_CTRL_MEMWR0: ctrl_memory_writer
 
  U_CTRL_MEMWR0: ctrl_memory_writer
 
    generic map(
 
    generic map(
 
      MEM_ADD_WIDTH => 14--: integer :=  14
 
      MEM_ADD_WIDTH => 14--: integer :=  14
 
    )
 
    )
 
    port map(
 
    port map(
 
      -- to memory
 
      -- to memory
 
      DAT_O_mem => DAT_O_memw, -- direct
 
      DAT_O_mem => DAT_O_memw, -- direct
 
      ADR_O_mem => memwr_out_adr,   --!
 
      ADR_O_mem => memwr_out_adr,
 
      CYC_O_mem => CYC_O_memw, -- direct
 
      CYC_O_mem => CYC_O_memw, -- direct
 
      STB_O_mem => STB_O_memw, -- direct
 
      STB_O_mem => STB_O_memw, -- direct
 
      ACK_I_mem => ACK_I_memw, -- direct
 
      ACK_I_mem => memwr_in_ack_mem,  -- direct
 
      WE_O_mem  => WE_O_memw, -- direct
 
      WE_O_mem  => WE_O_memw, -- direct
 
      -- to acquistion module
 
      -- to acquistion module
 
      DAT_I_adc => memwr_in_dat,    --!
 
      DAT_I_adc => memwr_in_dat,
 
      CYC_O_adc => CYC_O_adc, -- direct
 
      CYC_O_adc => memwr_out_cyc_daq,   -- direct
 
      STB_O_adc => memwr_stb,
 
      STB_O_adc => memwr_out_stb_daq,   -- direct
 
      ACK_I_adc => memwr_ack,
 
      ACK_I_adc => dskip_out_ack,
 
      WE_O_adc  => WE_O_adc, -- direct
 
 
 
      -- Common signals 
      -- Common signals 
      RST_I => RST_I_daq, -- direct
 
      RST_I => RST_I_daq, -- direct
 
      CLK_I => CLK_I_daq, -- direct
 
      CLK_I => CLK_I_daq, -- direct
 
      -- Internal
 
      -- Internal
 
      reset_I         => memwr_reset,
 
      reset_I         => memwr_reset,
 
      enable_I        => memwr_en,
 
      enable_I        => memwr_en,
 
      final_address_I => buffer_size,
 
      final_address_I => reg_buffer_size,
 
      finished_O      => memwr_finish,
 
      finished_O      => open,            -- !
 
      continuous_I    => memwr_continuous
 
      continuous_I    => reg_trigger_en
 
    );
 
    );
 
 
 
 
 
 
 
 
 
  U_CTRL_DSKIP0: ctrl_data_skipper
 
  U_CTRL_DSKIP0: ctrl_data_skipper
 
    generic map(
 
    generic map(
 
      SELECTOR_WIDTH    => 5,--: integer := 5 
      SELECTOR_WIDTH    => 5--: integer := 5 
    )
 
    )
 
    port map(
 
    port map(
 
      ack_O             => dskip_out_ack,
 
      ack_O             => dskip_out_ack,
 
      ack_I             => ACK_I_daq,
 
      ack_I             => ACK_I_daq, -- direct
 
      stb_I             => dskip_in_stb,
 
      stb_I             => memwr_out_stb_daq,
 
      selector_I        => reg_time_scale,
 
      selector_I        => reg_time_scale,
 
      enable_skipper_I  => reg_time_scale_en,
 
      enable_skipper_I  => reg_time_scale_en,
 
      reset_I           => RST_I_daq,
 
      reset_I           => dskip_reset,
 
      clk_I             => CLK_I_daq,
 
      clk_I             => CLK_I_daq, -- direct
 
      first_channel_I   => chsel_first_channel
 
      first_channel_I   => chsel_first_channel
 
    );
 
    );
 
 
 
 
 
 
 
 
 
  U_CTRL_CHSEL0: ctrl_channel_selector
 
  U_CTRL_CHSEL0: ctrl_channel_selector
 
    generic map(
 
    generic map(
 
      CHANNEL_WIDTH     => 4 --: integer := 4 -- number of channels 2**CHANNEL_WIDTH, max. 4
 
      CHANNEL_WIDTH     => 1 -- number of channels 2**CHANNEL_WIDTH, max. 4 
    )
 
    )
 
    port map(
 
    port map(
 
      channels_I        => reg_channels_selection,
 
      channels_I        => reg_channels_selection,
 
      channel_number_O  => chsel_channel,
 
      channel_number_O  => chsel_channel,
 
      first_channel_O   => chsel_first_channel,
 
      first_channel_O   => chsel_first_channel,
 
      clk_I             => CLK_I_daq,
 
      clk_I             => CLK_I_daq,
 
      enable_I          => chsel_en,
 
      enable_I          => '1',
 
      reset_I           => chsel_reset
 
      reset_I           => chsel_reset
 
    );
 
    );
 
 
 
 
 
 
 
 
 
 
 
 
 
  U_CTRL_TRIGGER0: ctrl_trigger_manager
 
  U_CTRL_TRIGGER0: ctrl_trigger_manager
 
    generic map(
 
    generic map(
 
      MEM_ADD_WIDTH   => 14,--:  integer := 14;
 
      MEM_ADD_WIDTH   => 14,--:  integer := 14;
 
      DATA_WIDTH      => 10,--:     integer := 10;
 
      DATA_WIDTH      => 10,--:     integer := 10;
 
      CHANNELS_WIDTH  => 1--: integer := 4
 
      CHANNELS_WIDTH  => 1--: integer := 4
 
    )
 
    )
 
    port map(
 
    port map(
 
      data_I          => DAT_I_daq,
 
      data_I          => DAT_I_daq(9 downto 0),
 
      channel_I       => chsel_channel,
 
      channel_I       => chsel_channel,
 
      trig_channel_I  => reg_trigger_channel,
 
      trig_channel_I  => reg_trigger_channel,
 
      address_I       => memwr_out_adr,
 
      address_I       => memwr_out_adr,
 
      final_address_I => reg_buffer_size,
 
      final_address_I => reg_buffer_size,
 
      offset_I        => reg_trigger_offset,
 
      offset_I        => reg_trigger_offset,
Line 288... Line 281... 
      trigger_O       => trigger_act,
 
      trigger_O       => trigger_act,
 
      address_O       => trigger_out_adr
 
      address_O       => trigger_out_adr
 
    );
 
    );
 
 
 
 
 
  -- reg_: signals from conf registers
 
  -- reg_: signals from conf registers
 
  U_CTRL_ADDASSMNT0: ctrl_address_assignments
 
  U_CTRL_ADDALLOC0: ctrl_address_allocation
 
    port map(
 
    port map(
 
      -- From port
 
      -- From port
 
      DAT_I_port        => DAT_I_port,
 
      DAT_I_port        => DAT_I_port,
 
      DAT_O_port        => DAT_O_port,
 
      DAT_O_port        => DAT_O_port,
 
      ADR_I_port        => ADR_I_port,
 
      ADR_I_port        => ADR_I_port,
Line 301... Line 294... 
      ACK_O_port        => ACK_O_port,
 
      ACK_O_port        => ACK_O_port,
 
      WE_I_port         => WE_I_port,
 
      WE_I_port         => WE_I_port,
 
      RST_I             => RST_I_port,
 
      RST_I             => RST_I_port,
 
      CLK_I             => CLK_I_port,
 
      CLK_I             => CLK_I_port,
 
      -- To internal 
      -- To internal 
      CYC_O_int         => cyc_to_outmgr,
 
      CYC_O_int         => outmgr_in_cyc,
 
      STB_O_int         => stb_to_outmgr,
 
      STB_O_int         => outmgr_in_stb,
 
      ACK_I_int         => ack_from_outmgr,
 
      ACK_I_int         => outmgr_out_akc,
 
      DAT_I_int         => dat_from_outmgr,
 
      DAT_I_int         => outmgr_out_dat,
 
      -- Internal          
      -- Internal          
      time_scale_O      => reg_time_scale,
 
      time_scale_O      => reg_time_scale,
 
      time_scale_en_O   => reg_time_scale_en,
 
      time_scale_en_O   => reg_time_scale_en,
 
      channels_sel_O    => reg_channels_selection,
 
      channels_sel_O    => reg_channels_selection,
 
      buffer_size_O     => reg_buffer_size,
 
      buffer_size_O     => reg_buffer_size,
Line 317... Line 310... 
      trigger_edge_O    => reg_trigger_edge,
 
      trigger_edge_O    => reg_trigger_edge,
 
      trigger_level_O   => reg_trigger_level,
 
      trigger_level_O   => reg_trigger_level,
 
      trigger_offset_O  => reg_trigger_offset,
 
      trigger_offset_O  => reg_trigger_offset,
 
      trigger_channel_O => reg_trigger_channel,
 
      trigger_channel_O => reg_trigger_channel,
 
 
 
 
 
      error_number_I    => "0000", -- not implemented yet
 
      error_number_I    => "000", -- not implemented yet
 
      data_channel_I    => data_channel_r,
 
 
 
      error_flag_I      => '0',   -- not implemented yet
 
      error_flag_I      => '0',   -- not implemented yet
 
 
 
 
 
 
 
      adc_conf_O        => dat_to_adc,
 
 
 
 
 
      start_O           => start,
 
      start_O           => start,
 
      continuous_O      => continuous,
 
      continuous_O      => continuous,
 
      running_I         => running,
 
      running_I         => running,
 
 
 
      write_in_adc_O    => write_in_adc,
 
      stop_O            => stop
 
      stop_O            => stop
 
    );
 
    );
 
 
 
 
 
  ------------------------------------------------------------------------------------------------
 
  ------------------------------------------------------------------------------------------------
 
 
 
  -- Assignments
 
 
 
  ADR_O_memw <= memwr_out_adr;
 
 
 
  ADR_O_daq <= '0' & chsel_channel(0) when strobe_adc = '0'
 
 
 
               else "10";
 
 
 
  DAT_O_daq <= dat_to_adc;
 
 
 
  CYC_O_daq <= strobe_adc or memwr_out_cyc_daq;
 
 
 
  STB_O_daq <= strobe_adc or memwr_out_stb_daq;
 
 
 
  WE_O_daq <= strobe_adc ;
 
 
 
 
 
 
 
 
 
 
 
  memwr_in_dat <= (15 downto 11 => '0') &  chsel_channel & DAT_I_daq(9 downto 0);
 
 
 
  memwr_in_ack_mem <= ACK_I_memw;
 
 
 
 
 
 
 
  ------------------------------------------------------------------------------------------------
 
  -- Machine
 
  -- Machine
 
  P_sm_comb: process ()
 
  P_sm_comb: process (present_state, reg_trigger_en, trigger_out_adr, memwr_out_adr, reg_trigger_en,
 
 
 
  memwr_in_ack_mem, outmgr_finish, continuous, ack_i_daq)
 
  begin
 
  begin
 
 
 
    -- signals from output manager are described in next process
 
    case present_state is
 
    case present_state is
 
      when ST_INIT =>
 
      when ST_INIT =>
 
 
 
 
 
        memwr_reset       <= '1';
 
        memwr_reset       <= '1';
 
        memwr_en          <= '0';
 
        memwr_en          <= '-';
 
        memwr_continuous  <= '-';
 
 
 
 
 
 
 
        dskip_reset   <= '1';
 
        dskip_reset   <= '1';
 
        dskip_en      <= '0';
 
 
 
 
 
 
 
        chsel_reset   <= '1';
 
        chsel_reset   <= '0';
 
        chsel_en      <= '0';
 
 
 
 
 
 
 
        trigger_reset <= '1';
 
        trigger_reset <= '1';
 
        trigger_en    <= '0';
 
        trigger_en    <= '-';
 
 
 
 
 
 
 
 
 
 
 
        running <= '1';
 
 
 
 
 
 
 
        strobe_adc <= '0';
 
 
 
 
 
 
 
        -- -- -- --
 
        next_state    <= ST_RUNNING;
 
        next_state    <= ST_RUNNING;
 
 
 
 
 
 
 
 
 
      when ST_RUNNING =>
 
      when ST_RUNNING =>
 
 
 
 
 
        memwr_reset       <= '0';
 
        memwr_reset       <= '0';
 
        memwr_en          <= ;
 
        if reg_trigger_en = '1' and trigger_out_adr = memwr_out_adr then
 
        memwr_continuous  <= ;
 
          memwr_en        <= '0';
 
 
 
        else
 
 
 
          memwr_en        <= '1';
 
 
 
        end if;
 
 
 
 
 
        dskip_reset   <= '0';
 
        dskip_reset   <= '0';
 
        dskip_en      <= reg_time_scale_en;
 
 
 
 
 
 
 
        chsel_reset   <= '0';
 
        chsel_reset   <= '0';
 
        chsel_en      <= dskip_out_ack;
 
 
 
 
 
 
 
        trigger_reset <= '0';
 
        trigger_reset <= '0';
 
        trigger_en    <= reg_trigger_en and memwr_ack;
 
        trigger_en    <= reg_trigger_en and memwr_in_ack_mem;
 
 
 
 
 
 
 
        running <= '1';
 
 
 
 
 
 
 
        strobe_adc <= '0';
 
 
 
 
 
 
 
        -- -- -- --
 
 
 
        if outmgr_finish = '1' then
 
 
 
          if continuous = '1' then
 
 
 
            next_state <= ST_INIT;
 
 
 
          else
 
 
 
            next_state <= ST_IDLE;
 
 
 
          end if;
 
 
 
        else
 
 
 
          next_state <= ST_RUNNING;
 
 
 
        end if;
 
 
 
 
 
 
 
      when ST_ADCWRITE_INIT =>
 
 
 
        memwr_reset       <= '1';
 
 
 
        memwr_en          <= '-';
 
 
 
 
 
 
 
        dskip_reset   <= '1';
 
 
 
 
 
 
 
        chsel_reset   <= '1';
 
 
 
 
 
 
 
        trigger_reset <= '1';
 
 
 
        trigger_en    <= '-';
 
 
 
 
 
 
 
        running <= '1';
 
 
 
 
 
 
 
        strobe_adc <= '0';
 
 
 
 
 
 
 
        -- -- -- --
 
 
 
        next_state <= ST_ADCWRITE;
 
 
 
 
 
 
 
 
 
 
 
      when ST_ADCWRITE =>
 
 
 
        memwr_reset       <= '1';
 
 
 
        memwr_en          <= '-';
 
 
 
 
 
 
 
        dskip_reset   <= '1';
 
 
 
 
 
 
 
        chsel_reset   <= '1';
 
 
 
 
 
 
 
        trigger_reset <= '1';
 
 
 
        trigger_en    <= '-';
 
 
 
 
 
 
 
        running <= '1';
 
 
 
 
 
 
 
        strobe_adc <= '1';
 
 
 
 
 
 
 
        -- -- -- --
 
 
 
        if ACK_I_daq = '1' then
 
 
 
          next_state <= ST_IDLE;
 
 
 
        else
 
 
 
          next_state <= ST_ADCWRITE;
 
 
 
        end if;
 
 
 
 
 
      when others =>  --ST_IDLE
 
      when others =>  --ST_IDLE
 
 
 
 
 
 
 
        memwr_reset       <= '1';
 
 
 
        memwr_en          <= '-';
 
 
 
 
 
 
 
        dskip_reset   <= '1';
 
 
 
 
 
 
 
        chsel_reset   <= '1';
 
 
 
 
 
 
 
        trigger_reset <= '1';
 
 
 
        trigger_en    <= '-';
 
 
 
 
 
 
 
        running <= '1';
 
 
 
 
 
 
 
        strobe_adc <= '0';
 
 
 
 
 
 
 
        -- -- -- --
 
 
 
        next_state    <= ST_IDLE;
 
    end case;
 
    end case;
 
 
 
 
 
  end process;
 
  end process;
 
 
 
 
 
 
 
 
 
 
 
 
 
  P_sm_clkd: process ()
 
  P_sm_clkd: process (RST_I_daq, stop, start, CLK_I_daq, next_state, write_in_adc)
 
  begin
 
  begin
 
 
 
 
 
    if RST_I_daq = '1' or stop = '1' then
 
    if RST_I_daq = '1' or stop = '1' then
 
      present_state <= ST_IDLE;
 
      present_state <= ST_IDLE;
 
    elsif start = '1' then
 
    elsif write_in_adc = '1' then
 
 
 
      present_state <= ST_ADCWRITE_INIT;
 
 
 
    elsif start = '1' and present_state /= ST_ADCWRITE and present_state /= ST_ADCWRITE_INIT then
 
      present_state <= ST_INIT;
 
      present_state <= ST_INIT;
 
    elsif CLK_I_daq'ecent and clk_I = '1' then
 
    elsif CLK_I_daq'event and CLK_I_daq = '1' then
 
      present_state <= next_state;
 
      present_state <= next_state;
 
    end if;
 
    end if;
 
 
 
 
 
 
 
 
 
  end process;
 
  end process;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  ------------------------------------------------------------------------------------------------
 
  ------------------------------------------------------------------------------------------------
 
  -- Output
 
  -- Output
 
 
 
 
 
  P_OUTMGR: process (RST_I_port, stop, CLK_I_port, CLK_I_port, present_state, trigger_act,
 
  P_OUTMGR: process (RST_I_port, stop, CLK_I_port, CLK_I_port, present_state, trigger_act,
 
  reg_trigger_en, memwr_out_adr, outmgr_en)
 
  reg_trigger_en, memwr_out_adr, outmgr_en)
 
    if RST_I_port = '1' or present_state = IDLE or present_state = INIT then
 
  begin
 
 
 
    if RST_I_port = '1' or present_state = ST_IDLE or present_state = ST_INIT then
 
      outmgr_load <= '0';
 
      outmgr_load <= '0';
 
      outmgr_en   <=  '0';
 
      outmgr_en   <=  '0';
 
    elsif CLK_I_port'event and CLK_I_port = '1' then
 
    elsif CLK_I_port'event and CLK_I_port = '1' then
 
      if present_state = ST_RUNNING and trigger_act = '1' or (reg_trigger_en = '0' and
 
      if stop = '1' then
 
      memwr_out_adr != conv_integer(0) ) then
 
        outmgr_load <=  '0';
 
 
 
        outmgr_en   <=  '0';
 
 
 
      elsif present_state = ST_RUNNING and ( trigger_act = '1' or (reg_trigger_en = '0' and
 
 
 
      memwr_out_adr /= 0 ) ) then
 
        outmgr_load <=  '1';
 
        outmgr_load <=  '1';
 
        outmgr_en   <=  '1';
 
        outmgr_en   <=  '1';
 
        -- load must be set only one cycle
 
        -- load must be set only one cycle
 
      elsif outmgr_en = '1' then
 
      elsif outmgr_en = '1' then
 
        load <= '0';
 
        outmgr_load <= '0';
 
      end if;
 
      end if;
 
    end if;
 
    end if;
 
  end process;
 
  end process;
 
 
 
 
 
  outmgr_initial_adr <= trigger_out_adr     when reg_trigger_en = '1' else
 
  outmgr_initial_adr <= trigger_out_adr     when reg_trigger_en = '1' else

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