| Line 338... |
Line 338... |
memwr_in_dat <= (15 downto 11 => '0') & chsel_channel & DAT_I_daq(9 downto 0);
|
memwr_in_dat <= (15 downto 11 => '0') & chsel_channel & DAT_I_daq(9 downto 0);
|
memwr_in_ack_mem <= ACK_I_memw;
|
memwr_in_ack_mem <= ACK_I_memw;
|
|
|
------------------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------------------
|
-- Machine
|
-- Machine
|
P_sm_comb: process (present_state, reg_trigger_en, trigger_out_adr, memwr_out_adr, reg_trigger_en,
|
P_sm_comb: process (present_state, reg_trigger_en, trigger_out_adr, memwr_out_adr,
|
memwr_in_ack_mem, outmgr_finish, continuous, ack_i_daq)
|
memwr_in_ack_mem, outmgr_finish, continuous, ack_i_daq)
|
begin
|
begin
|
-- signals from output manager are described in next process
|
-- signals from output manager are described in next process
|
case present_state is
|
case present_state is
|
when ST_INIT =>
|
when ST_INIT =>
|
| Line 405... |
Line 405... |
chsel_reset <= '1';
|
chsel_reset <= '1';
|
|
|
trigger_reset <= '1';
|
trigger_reset <= '1';
|
trigger_en <= '-';
|
trigger_en <= '-';
|
|
|
running <= '1';
|
running <= '1'; -- aviod an ack if there is a read/write from port
|
|
|
strobe_adc <= '0';
|
strobe_adc <= '0';
|
|
|
-- -- -- --
|
-- -- -- --
|
next_state <= ST_ADCWRITE;
|
next_state <= ST_ADCWRITE;
|
| Line 424... |
Line 424... |
chsel_reset <= '1';
|
chsel_reset <= '1';
|
|
|
trigger_reset <= '1';
|
trigger_reset <= '1';
|
trigger_en <= '-';
|
trigger_en <= '-';
|
|
|
running <= '1';
|
running <= '1'; -- aviod an ack if there is a read/write from port
|
|
|
strobe_adc <= '1';
|
strobe_adc <= '1';
|
|
|
-- -- -- --
|
-- -- -- --
|
if ACK_I_daq = '1' then
|
if ACK_I_daq = '1' then
|
| Line 447... |
Line 447... |
chsel_reset <= '1';
|
chsel_reset <= '1';
|
|
|
trigger_reset <= '1';
|
trigger_reset <= '1';
|
trigger_en <= '-';
|
trigger_en <= '-';
|
|
|
running <= '1';
|
running <= '0';
|
|
|
strobe_adc <= '0';
|
strobe_adc <= '0';
|
|
|
-- -- -- --
|
-- -- -- --
|
next_state <= ST_IDLE;
|
next_state <= ST_IDLE;
|
| Line 480... |
Line 480... |
|
|
|
|
------------------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------------------
|
-- Output
|
-- Output
|
|
|
P_OUTMGR: process (RST_I_port, stop, CLK_I_port, CLK_I_port, present_state, trigger_act,
|
P_OUTMGR: process (RST_I_port, stop, CLK_I_port, present_state, trigger_act,
|
reg_trigger_en, memwr_out_adr, outmgr_en)
|
reg_trigger_en, memwr_out_adr, outmgr_en)
|
begin
|
begin
|
if RST_I_port = '1' or present_state = ST_IDLE or present_state = ST_INIT then
|
-- load must be '1' only for one cycle, enable must be set until the end
|
|
if RST_I_port = '1' or present_state /= ST_RUNNING then
|
outmgr_load <= '0';
|
outmgr_load <= '0';
|
outmgr_en <= '0';
|
outmgr_en <= '0';
|
elsif CLK_I_port'event and CLK_I_port = '1' then
|
elsif CLK_I_port'event and CLK_I_port = '1' then
|
if stop = '1' then
|
if stop = '1' then
|
outmgr_load <= '0';
|
outmgr_load <= '0';
|
outmgr_en <= '0';
|
outmgr_en <= '0';
|
|
elsif outmgr_en = '1' then
|
|
outmgr_load <= '0';
|
elsif present_state = ST_RUNNING and ( trigger_act = '1' or (reg_trigger_en = '0' and
|
elsif present_state = ST_RUNNING and ( trigger_act = '1' or (reg_trigger_en = '0' and
|
memwr_out_adr /= 0 ) ) then
|
memwr_out_adr /= 0 ) ) then
|
outmgr_load <= '1';
|
outmgr_load <= '1';
|
outmgr_en <= '1';
|
outmgr_en <= '1';
|
-- load must be set only one cycle
|
-- load must be set only one cycle
|
elsif outmgr_en = '1' then
|
|
outmgr_load <= '0';
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
outmgr_initial_adr <= trigger_out_adr when reg_trigger_en = '1' else
|
outmgr_initial_adr <= trigger_out_adr when reg_trigger_en = '1' else
|
