| Line 133... |
Line 133... |
signal memwr_out_stb_daq: std_logic;
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signal memwr_out_stb_daq: std_logic;
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signal memwr_in_ack_mem: std_logic;
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signal memwr_in_ack_mem: std_logic;
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signal memwr_out_cyc_daq: std_logic;
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signal memwr_out_cyc_daq: std_logic;
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signal memwr_out_adr: std_logic_vector (13 downto 0);
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signal memwr_out_adr: std_logic_vector (13 downto 0);
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signal memwr_in_dat: std_logic_vector (15 downto 0);
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signal memwr_in_dat: std_logic_vector (15 downto 0);
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signal memwr_out_dat: std_logic_vector (15 downto 0);
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-- Outmgr
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-- Outmgr
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--signal outmgr_reset: std_logic;
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--signal outmgr_reset: std_logic;
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signal outmgr_en: std_logic;
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signal outmgr_en: std_logic;
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signal outmgr_load: std_logic;
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signal outmgr_load: std_logic;
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| Line 205... |
Line 206... |
generic map(
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generic map(
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MEM_ADD_WIDTH => 14--: integer := 14
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MEM_ADD_WIDTH => 14--: integer := 14
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)
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)
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port map(
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port map(
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-- to memory
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-- to memory
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DAT_O_mem => DAT_O_memw, -- direct
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DAT_O_mem => memwr_out_dat, -- direct
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ADR_O_mem => memwr_out_adr,
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ADR_O_mem => memwr_out_adr,
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CYC_O_mem => CYC_O_memw, -- direct
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CYC_O_mem => CYC_O_memw, -- direct
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STB_O_mem => STB_O_memw, -- direct
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STB_O_mem => STB_O_memw, -- direct
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ACK_I_mem => memwr_in_ack_mem, -- direct
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ACK_I_mem => memwr_in_ack_mem, -- direct
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WE_O_mem => WE_O_memw, -- direct
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WE_O_mem => WE_O_memw, -- direct
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| Line 265... |
Line 266... |
MEM_ADD_WIDTH => 14,--: integer := 14;
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MEM_ADD_WIDTH => 14,--: integer := 14;
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DATA_WIDTH => 10,--: integer := 10;
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DATA_WIDTH => 10,--: integer := 10;
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CHANNELS_WIDTH => 1 --: integer := 4
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CHANNELS_WIDTH => 1 --: integer := 4
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)
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)
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port map(
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port map(
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data_I => DAT_I_daq(9 downto 0),
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data_I => memwr_out_dat(9 downto 0), -- values beign writed in memory
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channel_I => chsel_channel,
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channel_I => memwr_out_dat(10 downto 10),
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trig_channel_I => reg_trigger_channel,
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trig_channel_I => reg_trigger_channel,
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address_I => memwr_out_adr,
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address_I => memwr_out_adr,
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final_address_I => reg_buffer_size,
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final_address_I => reg_buffer_size,
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offset_I => reg_trigger_offset,
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offset_I => reg_trigger_offset,
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level_I => reg_trigger_level,
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level_I => reg_trigger_level,
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| Line 325... |
Line 326... |
);
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);
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------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------
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-- Assignments
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-- Assignments
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ADR_O_memw <= memwr_out_adr;
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ADR_O_memw <= memwr_out_adr;
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DAT_O_memw <= memwr_out_dat;
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ADR_O_daq <= '0' & chsel_channel(0) when strobe_adc = '0'
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ADR_O_daq <= '0' & chsel_channel(0) when strobe_adc = '0'
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else "10";
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else "10";
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DAT_O_daq <= dat_to_adc;
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DAT_O_daq <= dat_to_adc;
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CYC_O_daq <= strobe_adc or memwr_out_cyc_daq;
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CYC_O_daq <= strobe_adc or memwr_out_cyc_daq;
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STB_O_daq <= strobe_adc or memwr_out_stb_daq;
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STB_O_daq <= strobe_adc or memwr_out_stb_daq;
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| Line 366... |
Line 369... |
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when ST_RUNNING =>
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when ST_RUNNING =>
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memwr_reset <= '0';
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memwr_reset <= '0';
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if reg_trigger_en = '1' and trigger_out_adr = memwr_out_adr then
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if reg_trigger_en = '1' and trigger_out_adr = memwr_out_adr and trigger_act = '1' then
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memwr_en <= '0';
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memwr_en <= '0';
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else
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else
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memwr_en <= '1';
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memwr_en <= '1';
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end if;
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end if;
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