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Line 22... |
----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--==================================================================================================
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--==================================================================================================
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-- TO DO
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-- TO DO
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-- · clean
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-- ·
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--==================================================================================================
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--==================================================================================================
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.math_real.all;
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use ieee.math_real.all;
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Line 171... |
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begin
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begin
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Instances
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-- Instances
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U_OUTMGR0: ctrl_output_manager
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U_CTRL_OUTMGR0: ctrl_output_manager
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generic map(
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generic map(
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MEM_ADD_WIDTH => 14 --: integer := 14
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MEM_ADD_WIDTH => 14 --: integer := 14
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)
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)
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port map(
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port map(
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-- MASTER (to memory)
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-- MASTER (to memory)
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Line 342... |
memwr_in_ack_mem <= ACK_I_memw;
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memwr_in_ack_mem <= ACK_I_memw;
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------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------
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-- Machine
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-- Machine
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P_sm_comb: process (present_state, reg_trigger_en, trigger_out_adr, memwr_out_adr,
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P_sm_comb: process (present_state, reg_trigger_en, trigger_out_adr, memwr_out_adr,
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memwr_in_ack_mem, outmgr_finish, continuous, ack_i_daq)
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memwr_in_ack_mem, outmgr_finish, continuous, ack_i_daq,next_status1,trigger_act)
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begin
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begin
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-- signals from output manager are described in next process
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-- signals from output manager are described in next process
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case present_state is
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case present_state is
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when ST_INIT =>
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when ST_INIT =>
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Line 359... |
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trigger_reset <= '1';
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trigger_reset <= '1';
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trigger_en <= '-';
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trigger_en <= '-';
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status(0) <= '1';
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status(0) <= '1';
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next_status1 <= not(next_status1); -- will be changed every buffer full read
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-- next_status1: above
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strobe_adc <= '0';
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strobe_adc <= '0';
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-- -- -- --
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-- -- -- --
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if outmgr_finish = '0' then
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next_state <= ST_RUNNING;
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next_state <= ST_RUNNING;
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-- if there is an error manager, influde an if for errors in parameters
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next_status1 <= not(status(1)); -- will be changed every buffer full read
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else
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next_state <= ST_INIT;
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next_status1 <= status(1);
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end if;
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-- if there is an error manager, include "if" for errors in parameters
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when ST_RUNNING =>
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when ST_RUNNING =>
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memwr_reset <= '0';
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memwr_reset <= '0';
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Line 476... |
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end process;
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end process;
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P_sm_clkd: process (RST_I_daq, stop, start, CLK_I_daq, next_state, write_in_adc)
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P_sm_clkd: process (RST_I_daq, stop, start, CLK_I_daq, next_state, write_in_adc,next_status1)
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begin
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begin
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if RST_I_daq = '1' then
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if RST_I_daq = '1' then
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present_state <= ST_IDLE;
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present_state <= ST_IDLE;
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status(1) <= '0';
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status(1) <= '0';
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elsif stop = '1' then
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elsif stop = '1' then
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present_state <= ST_IDLE;
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present_state <= ST_IDLE;
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status(1) <= '0';
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elsif write_in_adc = '1' then
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elsif write_in_adc = '1' then
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present_state <= ST_ADCWRITE_INIT;
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present_state <= ST_ADCWRITE_INIT;
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status(1) <= next_status1;
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elsif start = '1' and present_state /= ST_ADCWRITE and present_state /= ST_ADCWRITE_INIT then
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elsif start = '1' and present_state /= ST_ADCWRITE and present_state /= ST_ADCWRITE_INIT then
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present_state <= ST_INIT;
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present_state <= ST_INIT;
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status(1) <= next_status1;
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elsif CLK_I_daq'event and CLK_I_daq = '1' then
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elsif CLK_I_daq'event and CLK_I_daq = '1' then
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present_state <= next_state;
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present_state <= next_state;
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status(1) <= next_status1;
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status(1) <= next_status1;
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end if;
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end if;
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