| Line 119... |
Line 119... |
-- Using an address generator, commented
|
-- Using an address generator, commented
|
-- ADR_O_adc: out std_logic_vector (ADC_ADD_WIDTH - 1 downto 0);
|
-- ADR_O_adc: out std_logic_vector (ADC_ADD_WIDTH - 1 downto 0);
|
CYC_O_adc: out std_logic;
|
CYC_O_adc: out std_logic;
|
STB_O_adc: out std_logic;
|
STB_O_adc: out std_logic;
|
ACK_I_adc: in std_logic ;
|
ACK_I_adc: in std_logic ;
|
WE_O_adc: out std_logic;
|
--WE_O_adc: out std_logic;
|
----------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------
|
-- Common signals
|
-- Common signals
|
RST_I: in std_logic;
|
RST_I: in std_logic;
|
CLK_I: in std_logic;
|
CLK_I: in std_logic;
|
----------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------
|
| Line 134... |
Line 134... |
enable_I: in std_logic;
|
enable_I: in std_logic;
|
final_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
|
final_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
|
-- it is set when communication ends and remains until next restart or actual address change
|
-- it is set when communication ends and remains until next restart or actual address change
|
finished_O: out std_logic;
|
finished_O: out std_logic;
|
-- when counter finishes, restart
|
-- when counter finishes, restart
|
continuous_I: in std_logic;
|
continuous_I: in std_logic
|
);
|
);
|
end component ctrl_memory_writer;
|
end component ctrl_memory_writer;
|
|
|
|
|
component ctrl_data_skipper is
|
component ctrl_data_skipper is
|
| Line 206... |
Line 206... |
address_O: out std_logic_vector (MEM_ADD_WIDTH - 1 downto 0)
|
address_O: out std_logic_vector (MEM_ADD_WIDTH - 1 downto 0)
|
);
|
);
|
end component ctrl_trigger_manager;
|
end component ctrl_trigger_manager;
|
|
|
|
|
component ctrl_address_assignments is
|
component ctrl_address_allocation is
|
port(
|
port(
|
----------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------
|
-- From port
|
-- From port
|
DAT_I_port: in std_logic_vector (15 downto 0);
|
DAT_I_port: in std_logic_vector (15 downto 0);
|
DAT_O_port: out std_logic_vector (15 downto 0);
|
DAT_O_port: out std_logic_vector (15 downto 0);
|
| Line 229... |
Line 229... |
DAT_I_int: in std_logic_vector(15 downto 0);
|
DAT_I_int: in std_logic_vector(15 downto 0);
|
----------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------
|
-- Internal
|
-- Internal
|
start_O: out std_logic;
|
start_O: out std_logic;
|
continuous_O: out std_logic;
|
continuous_O: out std_logic;
|
trigger_en_O: out std_losugic;
|
trigger_en_O: out std_logic;
|
trigger_edge_O: out std_logic;
|
trigger_edge_O: out std_logic;
|
trigger_channel_O:out std_logic;
|
trigger_channel_O:out std_logic_vector(0 downto 0);
|
time_scale_O: out std_logic_vector(4 downto 0);
|
time_scale_O: out std_logic_vector(4 downto 0);
|
time_scale_en_O: out std_logic;
|
time_scale_en_O: out std_logic;
|
channels_sel_O: out std_logic_vector(1 downto 0);
|
channels_sel_O: out std_logic_vector(1 downto 0);
|
buffer_size_O: out std_logic_vector(13 downto 0);
|
buffer_size_O: out std_logic_vector(13 downto 0);
|
trigger_level_O: out std_logic_vector(9 downto 0);
|
trigger_level_O: out std_logic_vector(9 downto 0);
|
trigger_offset_O: out std_logic_vector(14 downto 0);
|
trigger_offset_O: out std_logic_vector(14 downto 0);
|
|
|
|
adc_conf_O: out std_logic_vector(15 downto 0);
|
|
|
error_number_I: in std_logic_vector (2 downto 0);
|
error_number_I: in std_logic_vector (2 downto 0);
|
data_channel_I: in std_logic;
|
|
running_I: in std_logic;
|
running_I: in std_logic;
|
error_flag_I: in std_logic;
|
error_flag_I: in std_logic;
|
|
|
|
write_in_adc_O: out std_logic;
|
stop_O: out std_logic
|
stop_O: out std_logic
|
);
|
);
|
end component ctrl_address_assignments;
|
end component ctrl_address_allocation;
|
|
|
|
|
|
component ctrl is
|
|
port(
|
|
------------------------------------------------------------------------------------------------
|
|
-- From port
|
|
DAT_I_port: in std_logic_vector (15 downto 0);
|
|
DAT_O_port: out std_logic_vector (15 downto 0);
|
|
ADR_I_port: in std_logic_vector (3 downto 0);
|
|
CYC_I_port: in std_logic;
|
|
STB_I_port: in std_logic;
|
|
ACK_O_port: out std_logic ;
|
|
WE_I_port: in std_logic;
|
|
CLK_I_port: in std_logic;
|
|
RST_I_port: in std_logic;
|
|
|
|
------------------------------------------------------------------------------------------------
|
|
-- To ADC
|
|
DAT_I_daq: in std_logic_vector (15 downto 0);
|
|
DAT_O_daq: out std_logic_vector (15 downto 0);
|
|
ADR_O_daq: out std_logic_vector (1 downto 0);
|
|
CYC_O_daq: out std_logic;
|
|
STB_O_daq: out std_logic;
|
|
ACK_I_daq: in std_logic ;
|
|
WE_O_daq: out std_logic;
|
|
|
|
CLK_I_daq: in std_logic;
|
|
RST_I_daq: in std_logic;
|
|
|
|
------------------------------------------------------------------------------------------------
|
|
-- To memory, A (writing) interface (Higer prioriry)
|
|
--DAT_I_memw: in std_logic_vector (15 downto 0);
|
|
DAT_O_memw: out std_logic_vector (15 downto 0);
|
|
ADR_O_memw: out std_logic_vector (13 downto 0);
|
|
CYC_O_memw: out std_logic;
|
|
STB_O_memw: out std_logic;
|
|
ACK_I_memw: in std_logic ;
|
|
WE_O_memw: out std_logic;
|
|
|
|
------------------------------------------------------------------------------------------------
|
|
-- To memory, B (reading) interface
|
|
DAT_I_memr: in std_logic_vector (15 downto 0);
|
|
--DAT_O_memr: out std_logic_vector (15 downto 0);
|
|
ADR_O_memr: out std_logic_vector (13 downto 0);
|
|
CYC_O_memr: out std_logic;
|
|
STB_O_memr: out std_logic;
|
|
ACK_I_memr: in std_logic ;
|
|
WE_O_memr: out std_logic
|
|
|
|
);
|
|
end component ctrl;
|
|
|
end package ctrl_pkg;
|
end package ctrl_pkg;
|
|
|
No newline at end of file
|
No newline at end of file
|
