| Line 1... |
Line 1... |
-------------------------------------------------------------------------------------------------100
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-------------------------------------------------------------------------------------------------100
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: data_skipper.vhd
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--| File: ctrl_data_skipper.vhd
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--| Version: 0.1
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--| Version: 0.12
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--| Tested in: Actel A3PE1500
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--| Tested in: Actel A3PE1500
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| CONTROL - Data skipper
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--| CONTROL - Data skipper
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--| It generates an enable signal for write acquisitions in memory.
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--| It generates an enable signal for write acquisitions in memory.
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--|
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--|
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.1 | jul-2009 | First testing
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--| 0.1 | jul-2009 | First testing
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--| 0.11 | jul-2009 | Added input signal indicating when it's selected the first channel
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--| 0.12 | jul-2009 | Optimized
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright © 2009, Facundo Aguilera.
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--| Copyright © 2009, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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| Line 38... |
Line 41... |
use work.ctrl_pkg.all;
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use work.ctrl_pkg.all;
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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entity data_skipper is
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entity ctrl_data_skipper is
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generic(
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generic(
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-- max losses = 2**(2**SELECTOR_WIDTH). (i.e., if SELECTOR_WIDTH = 5: 4.2950e+09)
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-- max losses = 2**(2**SELECTOR_WIDTH). (i.e., if SELECTOR_WIDTH = 5: 4.2950e+09)
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SELECTOR_WIDTH: integer := 5
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SELECTOR_WIDTH: integer := 5
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);
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);
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port(
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port(
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| Line 53... |
Line 56... |
-- selector from register, equation: losses = 2**(selector_I + 1) * enable_skipper_I
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-- selector from register, equation: losses = 2**(selector_I + 1) * enable_skipper_I
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selector_I: in std_logic_vector(SELECTOR_WIDTH-1 downto 0);
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selector_I: in std_logic_vector(SELECTOR_WIDTH-1 downto 0);
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-- enable from register
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-- enable from register
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enable_skipper_I: in std_logic;
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enable_skipper_I: in std_logic;
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-- common signals
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-- common signals
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reset_I, clk_I: in std_logic
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reset_I, clk_I: in std_logic;
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first_channel_I: in std_logic
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);
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);
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end entity data_skipper;
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end ctrl_entity data_skipper;
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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architecture ARCH10 of data_skipper is
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architecture ARCH10 of ctrl_data_skipper is
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signal count: std_logic_vector( integer(2**real(SELECTOR_WIDTH))-1 downto 0);
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signal count: std_logic_vector( integer(2**real(SELECTOR_WIDTH))-1 downto 0);
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signal decoded: std_logic_vector( integer(2**real(SELECTOR_WIDTH))-1 downto 0);
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signal decoded: std_logic_vector( integer(2**real(SELECTOR_WIDTH))-1 downto 0);
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signal anded: std_logic_vector( integer(2**real(SELECTOR_WIDTH))-1 downto 0);
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signal reset_count: std_logic;
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signal reset_count: std_logic;
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signal match: std_logic;
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signal match: std_logic;
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signal enable_count: std_logic;
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signal enable_count: std_logic;
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|
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begin
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begin
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|
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U_COUNTER0: generic_counter
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U_COUNTER0: generic_counter
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generic map(
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generic map(
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OUTPUT_WIDTH => integer(2**real(SELECTOR_WIDTH)) -- Output width for counter.
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OUTPUT_WIDTH => integer(2**real(SELECTOR_WIDTH)) -- Output width for counter.
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| Line 89... |
Line 96... |
enable_I => enable_skipper_I,
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enable_I => enable_skipper_I,
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data_I => selector_I,
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data_I => selector_I,
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decoded_O => decoded
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decoded_O => decoded
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);
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);
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|
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anded <= decoded and count;
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match <= '1' when decoded <= count else
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match <= '1' when anded = std_logic_vector(to_unsigned(0,integer(2**real(SELECTOR_WIDTH)))) else
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'0' ;
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'0' ;
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reset_count <= match or reset_I;
|
|
enable_count <= stb_I and ack_I and enable_skipper_I;
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reset_count <= reset_I;
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enable_count <= stb_I and ack_I and enable_skipper_I and first_channel_I;
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|
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ack_O <= stb_I and ack_I and (match or not(enable_skipper_I)) and not(reset_I);
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ack_O <= stb_I and ack_I and (match or not(enable_skipper_I)) and not(reset_I);
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|
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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