| Line 1... |
Line 1... |
-------------------------------------------------------------------------------------------------100
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-------------------------------------------------------------------------------------------------100
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--| Modular Oscilloscope
|
--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: memory_writer.vhd
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--| File: ctrl_memory_writer.vhd
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--| Version: 0.1
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--| Version: 0.1
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--| Tested in: Actel A3PE1500
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--| Tested in: Actel A3PE1500
|
--|-------------------------------------------------------------------------------------------------
|
--|-------------------------------------------------------------------------------------------------
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--| Description:
|
--| Description:
|
--| CONTROL - Memory writer
|
--| CONTROL - Memory writer
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| Line 34... |
Line 34... |
|
|
|
|
|
|
----------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------
|
entity memory_writer is
|
entity ctrl_memory_writer is
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generic(
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generic(
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MEM_ADD_WIDTH: integer := 14
|
MEM_ADD_WIDTH: integer := 14
|
);
|
);
|
port(
|
port(
|
------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------
|
| Line 65... |
Line 65... |
RST_I: in std_logic;
|
RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
|
|
|
------------------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------------------
|
-- Internal
|
-- Internal
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-- reset counter(memory address) to 0
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-- reset memory address to 0
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reset_I: in std_logic;
|
reset_I: in std_logic;
|
-- read in clk edge from the actual address ('0' means pause, '1' means continue)
|
-- read in clk edge from the actual address ('0' means pause, '1' means continue)
|
enable_I: in std_logic;
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enable_I: in std_logic;
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-- buffer starts and ends here
|
|
-- when the buffer arrives here, address is changed to 0 (buffer size)
|
|
final_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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final_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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-- address wich is being writed by control
|
|
-- stop_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
|
|
-- it is set when communication ends and remains until next restart or actual address change
|
-- it is set when communication ends and remains until next restart or actual address change
|
finished_O: out std_logic;
|
finished_O: out std_logic;
|
-- When counter finishes, restart
|
-- when counter finishes, restart
|
continuous_I: in std_logic;
|
continuous_I: in std_logic;
|
|
|
|
|
);
|
);
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end entity memory_writer;
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end entity ctrl_memory_writer;
|
|
|
|
|
|
|
|
|
----------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------
|
architecture ARCH11 of output_manager is
|
architecture ARCH11 of ctrl_output_manager is
|
|
|
type DataStatusType is (
|
type DataStatusType is (
|
INIT,
|
INIT,
|
WORKING
|
WORKING
|
);
|
);
|
| Line 108... |
Line 100... |
signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
|
signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
|
signal s_finished, s_STB_adc, s_STB_mem: std_logic; -- previous to outputs
|
signal s_finished, s_STB_adc, s_STB_mem: std_logic; -- previous to outputs
|
|
|
begin
|
begin
|
--------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------
|
-- Instantiations
|
-- Instances
|
U_COUNTER0: generic_counter
|
U_COUNTER0: generic_counter
|
generic map(
|
generic map(
|
OUTPUT_WIDTH => MEM_ADD_WIDTH -- Output width for counter.
|
OUTPUT_WIDTH => MEM_ADD_WIDTH -- Output width for counter.
|
)
|
)
|
port map(
|
port map(
|
| Line 151... |
Line 143... |
|
|
-- Lock interface when working
|
-- Lock interface when working
|
P_cyc_signals: process (clk_I, enable_count, ACK_I_adc, ACK_I_mem)
|
P_cyc_signals: process (clk_I, enable_count, ACK_I_adc, ACK_I_mem)
|
begin
|
begin
|
if CLK_I'event and CLK_I = '1' then
|
if CLK_I'event and CLK_I = '1' then
|
if enable_I /= '1' or reset_I = '1' then
|
if enable_I = '0' or reset_I = '1' then
|
CYC_O_adc <= '0'; CYC_O_mem <= '0';
|
CYC_O_adc <= '0'; CYC_O_mem <= '0';
|
else
|
else
|
CYC_O_adc <= '1'; CYC_O_mem <= '1';
|
CYC_O_adc <= '1'; CYC_O_mem <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
