| Line 87... |
Line 87... |
----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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architecture ARCH12 of ctrl_memory_writer is
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architecture ARCH12 of ctrl_memory_writer is
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type DataStatusType is (
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type DataStatusType is (
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FINISHED,
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FINISHED,
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INIT,
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-- INIT,
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WORKING
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WORKING
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);
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);
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signal data_status: DataStatusType;
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signal data_status: DataStatusType;
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Line 126... |
data_status = WORKING and
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data_status = WORKING and
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s_STB_mem = '1' and
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s_STB_mem = '1' and
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ACK_I_mem = '1'
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ACK_I_mem = '1'
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else
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else
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'0';
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'0';
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reset_count <= '1' when reset_I = '1' or s_finished = '1' else
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reset_count <= '1' when reset_I = '1' or (s_finished = '1' and enable_count = '1') else
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'0';
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'0';
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-- outputs
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-- outputs
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finished_O <= s_finished;
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finished_O <= s_finished;
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STB_O_adc <= s_STB_adc and enable_I; -- !
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STB_O_adc <= s_STB_adc and enable_I; -- !
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| Line 160... |
Line 160... |
P_stb_signals: process (CLK_I, reset_I, data_status, s_STB_adc, s_STB_mem, ACK_I_adc, ACK_I_mem)
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P_stb_signals: process (CLK_I, reset_I, data_status, s_STB_adc, s_STB_mem, ACK_I_adc, ACK_I_mem)
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begin
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begin
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if CLK_I'event and CLK_I = '1' then
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if CLK_I'event and CLK_I = '1' then
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if reset_I = '1' or RST_I = '1' then
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if reset_I = '1' or RST_I = '1' then
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data_status <= INIT;
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data_status <= WORKING;
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s_STB_adc <= '0';
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s_STB_adc <= '0';
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s_STB_mem <= '0';
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s_STB_mem <= '0';
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data <= (others => '0');
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data <= (others => '0');
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elsif enable_I = '1' then
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elsif enable_I = '1' then
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case data_status is
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case data_status is
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when INIT =>
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-- when INIT =>
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-- this state is only necessary when there are adc convertions in every clock
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-- -- this state is only necessary when there are adc convertions in every clock
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-- (for the first convertion)
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-- -- (for the first convertion)
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s_STB_adc <= '1';
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-- s_STB_adc <= '1';
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s_STB_mem <= '1';
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-- s_STB_mem <= '1';
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data_status <= WORKING;
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-- data_status <= WORKING;
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-- data <= DAT_I_adc; -- save data
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when WORKING =>
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when WORKING =>
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if s_STB_adc = '1' and ACK_I_adc = '1' then
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if ACK_I_adc = '1' then
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s_STB_mem <= '1'; -- strobe when adc ack
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s_STB_mem <= '1'; -- strobe when adc ack
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data <= DAT_I_adc; -- save data
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data <= DAT_I_adc; -- save data
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elsif s_STB_mem = '1' and ACK_I_mem = '1' then
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elsif s_STB_mem = '1' and ACK_I_mem = '1' then
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s_STB_mem <= '0';
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s_STB_mem <= '0';
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end if;
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end if;
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if s_STB_mem = '1' and ACK_I_mem = '1' then
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-- if s_STB_mem = '1' and ACK_I_mem = '1' then
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s_STB_adc <= '1'; -- strobe when mem ack
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s_STB_adc <= '1'; -- strobe when mem ack
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elsif s_STB_adc = '1' and ACK_I_adc = '1' then
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-- elsif s_STB_adc = '1' and ACK_I_adc = '1' then
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s_STB_adc <= '0';
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-- s_STB_adc <= '0';
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end if;
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-- end if;
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if continuous_I = '0' and s_finished = '1' then
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if continuous_I = '0' and reset_count = '1' then
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data_status <= FINISHED;
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data_status <= FINISHED;
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end if;
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end if;
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when others => -- FINISHED
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when others => -- FINISHED
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s_STB_adc <= '0';
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s_STB_adc <= '0';
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