| Line 1... |
Line 1... |
-------------------------------------------------------------------------------------------------100
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-------------------------------------------------------------------------------------------------100
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: output_manager.vhd
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--| File: output_manager.vhd
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--| Version: 0.3
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--| Version: 0.31
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--| Tested in: Actel A3PE1500
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--| Tested in: Actel A3PE1500
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| CONTROL - Output manager
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--| CONTROL - Output manager
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--| This is a pseudo buffer, wich reads a memory incrementaly under certain parameters.
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--| This is a pseudo buffer, wich reads a memory incrementaly under certain parameters.
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| Line 13... |
Line 13... |
--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.1 | jun-2009 | First testing
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--| 0.1 | jun-2009 | First testing
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--| 0.2 | jul-2009 | Two levels internal buffer
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--| 0.2 | jul-2009 | Two levels internal buffer
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--| 0.3 | jul-2009 | One level internal buffer and only one clock
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--| 0.3 | jul-2009 | One level internal buffer and only one clock
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--| 0.31 | jul-2009 | Internal WE signals
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright ® 2009, Facundo Aguilera.
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--| Copyright © 2009, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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|
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--| Wishbone Rev. B.3 compatible
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--==================================================================================================
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-- TODO
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-- TODO
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-- Config WE signals
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-- · Spped up address_counter (with Actel SmartGen).
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--==================================================================================================
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-- This first release
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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| Line 78... |
Line 79... |
-- buffer starts and ends here
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-- buffer starts and ends here
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initial_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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initial_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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-- when the buffer arrives here, address is changed to 0 (buffer size)
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-- when the buffer arrives here, address is changed to 0 (buffer size)
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final_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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final_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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-- address wich is being writed by control
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-- address wich is being writed by control
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-- stop_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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stop_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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-- it is set when communication ends and remains until next restart or actual address change
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-- it is set when communication ends and remains until next restart or actual address change
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finish: out std_logic
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finish: out std_logic
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);
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);
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| Line 91... |
Line 92... |
----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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architecture ARCH11 of output_manager is
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architecture ARCH11 of output_manager is
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|
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type DataStatusType is (
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type DataStatusType is (
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RESET,
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RESET,
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INIT, -- when restartet
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INIT, -- when restartet
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READY, -- data available to be read
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READY, -- data available to be read
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READ -- data was read from port, read next from memory
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READ -- data was read from port, read next from memory
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| Line 157... |
Line 160... |
--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Data read
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-- Data read
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ADR_O_mem <= address_counter;
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ADR_O_mem <= address_counter;
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s_finish <= '1' when address_counter = initial_address and data_status /= INIT else
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s_finish <= '1' when address_counter = initial_address and data_status /= INIT else
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'0';
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'0';
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enable_read <= enable and not(s_finish);
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enable_read <= '1' when enable = '1' and s_finish = '0' and address_counter /= stop_address
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else '0';
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finish <= s_finish;
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finish <= s_finish;
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WE_O_mem <= '0' ;
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WE_O_mem <= '0' ;
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|
|
|
|
|
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P_read: process(CLK_I, data_status, initial_address, address_counter, data, enable_read,
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P_read: process(CLK_I, data_status, initial_address, address_counter, data, enable_read,
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ACK_I_mem, WE_I_port)
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ACK_I_mem, WE_I_port)
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begin
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begin
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|
|
|
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-- Clocked signals
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-- Clocked signals
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if (CLK_I'event and CLK_I = '1') then
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if (CLK_I'event and CLK_I = '1') then
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case data_status is
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case data_status is
|
|
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when RESET =>
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when RESET =>
|
|
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data <= (others => '0');
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data <= (others => '0');
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address_counter <= initial_address;
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address_counter <= initial_address;
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|
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when READY =>
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when READY =>
|
|
|
