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Line 1... |
-------------------------------------------------------------------------------------------------100
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-------------------------------------------------------------------------------------------------100
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: output_manager.vhd
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--| File: output_manager.vhd
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--| Version: 0.31
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--| Version: 0.5
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--| Tested in: Actel A3PE1500
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--| Tested in: Actel A3PE1500
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| CONTROL - Output manager
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--| CONTROL - Output manager
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--| This is a pseudo buffer, wich reads a memory incrementaly under certain parameters.
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--| Reads a memory incrementaly under certain parameters.
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--|
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--|
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.1 | jun-2009 | First testing
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--| 0.1 | jun-2009 | First testing
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--| 0.2 | jul-2009 | Two levels internal buffer
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--| 0.2 | jul-2009 | Two levels internal buffer
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--| 0.3 | jul-2009 | One level internal buffer and only one clock
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--| 0.3 | jul-2009 | One level internal buffer and only one clock
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--| 0.31 | jul-2009 | Internal WE signals
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--| 0.31 | jul-2009 | Internal WE signals
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--| 0.5 | jul-2009 | Architecture completely renovated (reduced)
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright © 2009, Facundo Aguilera.
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--| Copyright © 2009, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--==================================================================================================
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--==================================================================================================
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-- TODO
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-- TODO
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-- · Spped up address_counter (with Actel SmartGen).
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-- · Spped up address_counter.
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-- · Test new architecture
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--==================================================================================================
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--==================================================================================================
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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| Line 70... |
Line 72... |
RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------
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-- Internal
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-- Internal
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-- reset counter to initial address, or load it
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load: in std_logic;
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load_I: in std_logic;
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-- start count from the actual address ('0' means pause, '1' means continue)
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-- load initial address
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enable: in std_logic;
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enable_I: in std_logic;
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-- continue reading from the actual address ('0' means pause, '1' means continue)
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initial_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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-- buffer starts and ends here
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-- buffer starts and ends here
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initial_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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biggest_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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-- when the buffer arrives here, address is changed to 0 (buffer size)
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-- when the buffer arrives here, address is changed to 0 (buffer size)
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final_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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pause_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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-- address wich is being writed by control
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-- address wich is being writed by control
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stop_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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-- it is set when communication ends and remains until next restart or actual address change
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finish: out std_logic
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finish_O: out std_logic
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-- it is set when communication ends and remains until next restart or actual address change
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);
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);
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end entity output_manager;
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end entity output_manager;
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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architecture ARCH11 of output_manager is
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architecture ARCH20 of output_manager is
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type DataStatusType is (
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RESET,
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INIT, -- when restartet
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READY, -- data available to be read
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READ -- data was read from port, read next from memory
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);
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signal data_status: DataStatusType; -- comunicates status between both ports
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signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
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signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
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signal data: std_logic_vector(15 downto 0);
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signal enable_read: std_logic;
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signal enable_read: std_logic;
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signal s_finish: std_logic;
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signal enable_count: std_logic;
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signal s_finish: std_logic; -- register previous (and equal) to output
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begin
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begin
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Data status resolution
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-- Wishbone signals
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P_status: process(CLK_I, RST_I, load, WE_I_port)
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begin
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if (CLK_I'event and CLK_I = '1') then
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if RST_I = '1' or load = '1' then
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data_status <= RESET;
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else
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case data_status is
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when RESET =>
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data_status <= INIT;
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when INIT =>
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if ACK_I_mem = '1' and enable_read = '1' then
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data_status <= READY;
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end if;
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DAT_O_port <= DAT_I_mem;
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CYC_O_mem <= CYC_I_port;
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STB_O_mem <= STB_I_port and enable_read;
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ACK_O_port <= ACK_I_mem;
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ADR_O_mem <= address_counter;
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WE_O_mem <= '0' ;
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when READ =>
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--------------------------------------------------------------------------------------------------
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-- Status signals
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if ACK_I_mem = '1' and enable_read = '1' and (STB_I_port /= '1' or CYC_I_port /= '1' or
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enable_read <= '1' when enable_I = '1' and s_finish = '0' and address_counter /= pause_address_I
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WE_I_port /= '0')
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and WE_I_port = '0'
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then
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else '0';
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data_status <= READY;
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end if;
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-- STB_I_port /= '1' or CYC_I_port /= '1': forwarding
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when others => -- (when READY)
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enable_count <= CYC_I_port and STB_I_port and ACK_I_mem and enable_read;
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if STB_I_port = '1' and CYC_I_port = '1' and WE_I_port = '0' then
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finish_O <= s_finish;
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data_status <= READ;
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end if;
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end case;
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P_finish: process ( CLK_I, RST_I, address_counter, initial_address_I, load_I)
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begin
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if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
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if RST_I = '1' then
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s_finish <= '1';
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elsif load_I = '1' then
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s_finish <= '0';
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elsif address_counter = initial_address_I then
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s_finish <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Data read
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-- Address counter
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ADR_O_mem <= address_counter;
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s_finish <= '1' when address_counter = initial_address and data_status /= INIT else
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'0';
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enable_read <= '1' when enable = '1' and s_finish = '0' and address_counter /= stop_address
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else '0';
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finish <= s_finish;
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P_count: process(CLK_I, address_counter, enable_count, load_I)
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WE_O_mem <= '0' ;
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P_read: process(CLK_I, data_status, initial_address, address_counter, data, enable_read,
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ACK_I_mem, WE_I_port)
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begin
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begin
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if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
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if load_I = '1' then
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-- Clocked signals
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address_counter <= initial_address_I;
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if (CLK_I'event and CLK_I = '1') then
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elsif enable_count = '1' then
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case data_status is
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if address_counter >= biggest_address_I then
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when RESET =>
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data <= (others => '0');
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address_counter <= initial_address;
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when READY =>
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if enable_read = '1' and ACK_I_mem = '1' and CYC_I_port = '1' and STB_I_port = '1' then
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-- (forwarding)
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data <= DAT_I_mem;
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if address_counter < final_address then
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address_counter <= address_counter + 1;
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else
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address_counter <= (others => '0');
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address_counter <= (others => '0');
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end if;
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else
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else
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data <= data;
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address_counter <= address_counter;
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end if;
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when others => -- (when INIT or READ)
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if enable_read = '1' and ACK_I_mem = '1' then
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data <= DAT_I_mem;
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if address_counter < final_address then
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address_counter <= address_counter + 1;
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address_counter <= address_counter + 1;
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else
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address_counter <= (others => '0');
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end if;
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end if;
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end if;
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end case;
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end if;
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-- Cominational signals
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case data_status is
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when RESET =>
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STB_O_mem <= '0';
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CYC_O_mem <= '0';
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when READY =>
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if enable_read = '1' and CYC_I_port = '1' and STB_I_port = '1' and WE_I_port = '0' then
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-- (forwarding)
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STB_O_mem <= '1';
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CYC_O_mem <= '1';
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else
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STB_O_mem <= '0';
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CYC_O_mem <= '0';
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end if;
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end if;
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when others => -- (when INIT or READ)
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if enable_read = '1' then
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STB_O_mem <= '1';
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CYC_O_mem <= '1';
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else
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STB_O_mem <= '0';
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CYC_O_mem <= '0';
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end if;
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end if;
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end case;
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end process;
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end process;
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--------------------------------------------------------------------------------------------------
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-- Read from port interface
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ACK_O_port <= '1' when (CYC_I_port = '1' and STB_I_port = '1' and WE_I_port = '0') and
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(data_status = READY or
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(data_status = READ and ACK_I_mem = '1' and enable_read = '1' )) else
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'0';
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-- data_status = READ and ACK_I_mem = '1' and enable_read = '1': forwarding
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DAT_O_port <= data;
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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