| Line 1... |
Line 1... |
-------------------------------------------------------------------------------------------------100
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-------------------------------------------------------------------------------------------------100
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: output_manager.vhd
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--| File: ctrl_output_manager.vhd
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--| Version: 0.5
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--| Version: 0.5
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--| Tested in: Actel A3PE1500
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--| Tested in: Actel A3PE1500
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| CONTROL - Output manager
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--| CONTROL - Output manager
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--| Reads a memory incrementaly under certain parameters.
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--| Reads a memory incrementaly under certain parameters.
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--|
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--|
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| Line 25... |
Line 26... |
----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--==================================================================================================
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--==================================================================================================
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-- TODO
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-- TODO
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-- · Spped up address_counter.
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-- · Spped up address_counter
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-- · Test new architecture
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-- · Test new architecture
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--==================================================================================================
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--==================================================================================================
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library ieee;
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library ieee;
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| Line 39... |
Line 40... |
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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entity output_manager is
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entity ctrl_output_manager is
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generic(
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generic(
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MEM_ADD_WIDTH: integer := 14
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MEM_ADD_WIDTH: integer := 14
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);
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);
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port(
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port(
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------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------
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| Line 92... |
Line 93... |
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finish_O: out std_logic
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finish_O: out std_logic
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-- it is set when communication ends and remains until next restart or actual address change
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-- it is set when communication ends and remains until next restart or actual address change
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|
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);
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);
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end entity output_manager;
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end entity ctrl_output_manager;
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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architecture ARCH20 of output_manager is
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architecture ARCH20 of ctrl_output_manager is
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|
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signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
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signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
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signal enable_read: std_logic;
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signal enable_read: std_logic;
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signal enable_count: std_logic;
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signal enable_count: std_logic;
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signal s_finish: std_logic; -- register previous (and equal) to output
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signal s_finish: std_logic; -- register previous (and equal) to output
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signal init: std_logic; -- register
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begin
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begin
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|
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Wishbone signals
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-- Wishbone signals
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DAT_O_port <= DAT_I_mem;
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DAT_O_port <= DAT_I_mem;
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CYC_O_mem <= CYC_I_port;
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CYC_O_mem <= CYC_I_port;
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STB_O_mem <= STB_I_port and enable_read;
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STB_O_mem <= STB_I_port and enable_read;
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ACK_O_port <= ACK_I_mem;
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ACK_O_port <= ACK_I_mem;
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ADR_O_mem <= address_counter;
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ADR_O_mem <= address_counter;
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WE_O_mem <= '0' ;
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WE_O_mem <= '0' ;
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|
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Status signals
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-- Status signals
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enable_read <= '1' when enable_I = '1' and WE_I_port = '0' and s_finish = '0' and
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enable_read <= '1' when enable_I = '1' and s_finish = '0' and address_counter /= pause_address_I
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(address_counter /= pause_address_I or init = '1')
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and WE_I_port = '0'
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else '0';
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else '0';
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enable_count <= CYC_I_port and STB_I_port and ACK_I_mem and enable_read;
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enable_count <= CYC_I_port and STB_I_port and ACK_I_mem and enable_read;
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|
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finish_O <= s_finish;
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finish_O <= s_finish;
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| Line 132... |
Line 131... |
P_finish: process ( CLK_I, RST_I, address_counter, initial_address_I, load_I)
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P_finish: process ( CLK_I, RST_I, address_counter, initial_address_I, load_I)
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begin
|
begin
|
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
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if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
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if RST_I = '1' then
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if RST_I = '1' then
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s_finish <= '1';
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s_finish <= '1';
|
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init <= '0';
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elsif load_I = '1' then
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elsif load_I = '1' then
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s_finish <= '0';
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s_finish <= '0';
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elsif address_counter = initial_address_I then
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init <= '1';
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elsif address_counter + 1 = initial_address_I then
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s_finish <= '1';
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s_finish <= '1';
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init <= '0';
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else
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init <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
|
|
|
--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Address counter
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-- Address counter
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|
|
P_count: process(CLK_I, address_counter, enable_count, load_I)
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P_count: process(CLK_I, address_counter, enable_count, load_I)
|
begin
|
begin
|
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
|
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
|
if load_I = '1' then
|
if load_I = '1' then
|
address_counter <= initial_address_I;
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address_counter <= initial_address_I;
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elsif enable_count = '1' then
|
elsif enable_count = '1' and address_counter >= biggest_address_I then
|
if address_counter >= biggest_address_I then
|
|
address_counter <= (others => '0');
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address_counter <= (others => '0');
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else
|
elsif enable_count = '1' then
|
address_counter <= address_counter + 1;
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address_counter <= address_counter + 1;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
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end process;
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end process;
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|
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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