| Line 1... |
Line 1... |
-------------------------------------------------------------------------------------------------100
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-------------------------------------------------------------------------------------------------100
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: ctrl_output_manager.vhd
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--| File: ctrl_output_manager.vhd
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--| Version: 0.5
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--| Version: 0.54
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--| Tested in: Actel A3PE1500
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--| Tested in: Actel A3PE1500
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| CONTROL - Output manager
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--| CONTROL - Output manager
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| Line 16... |
Line 16... |
--| 0.1 | jun-2009 | First testing
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--| 0.1 | jun-2009 | First testing
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--| 0.2 | jul-2009 | Two levels internal buffer
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--| 0.2 | jul-2009 | Two levels internal buffer
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--| 0.3 | jul-2009 | One level internal buffer and only one clock
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--| 0.3 | jul-2009 | One level internal buffer and only one clock
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--| 0.31 | jul-2009 | Internal WE signals
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--| 0.31 | jul-2009 | Internal WE signals
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--| 0.5 | jul-2009 | Architecture completely renovated (reduced)
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--| 0.5 | jul-2009 | Architecture completely renovated (reduced)
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--| 0.54 | aug-2009 | New finish_O and init flag behavior
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright © 2009, Facundo Aguilera.
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--| Copyright © 2009, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--==================================================================================================
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--==================================================================================================
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-- TO DO
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-- TO DO
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-- · Spped up address_counter
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-- NO Speed up address_counter
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-- · Test new architecture
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-- OK Full test of new architecture
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-- OK Fix default value of s_finish signal
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-- · General speed up
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--==================================================================================================
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--==================================================================================================
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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| Line 97... |
Line 100... |
);
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);
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end entity ctrl_output_manager;
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end entity ctrl_output_manager;
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|
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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architecture ARCH20 of ctrl_output_manager is
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architecture ARCH22 of ctrl_output_manager is
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|
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signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
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signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
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signal enable_read: std_logic;
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signal enable_read: std_logic;
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signal enable_count: std_logic;
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signal enable_count: std_logic;
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signal s_finish: std_logic; -- register previous (and equal) to output
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signal s_finish: std_logic; -- register previous (and equal) to output
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| Line 118... |
Line 121... |
ADR_O_mem <= address_counter;
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ADR_O_mem <= address_counter;
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WE_O_mem <= '0' ;
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WE_O_mem <= '0' ;
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|
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Status signals
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-- Status signals
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-- there is an init signal because in the first read, address_counter may be = to pause_address_I
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enable_read <= '1' when enable_I = '1' and WE_I_port = '0' and s_finish = '0' and
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enable_read <= '1' when enable_I = '1' and WE_I_port = '0' and s_finish = '0' and
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(address_counter /= pause_address_I or init = '1')
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(address_counter /= pause_address_I or init = '1')
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else '0';
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else '0';
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enable_count <= CYC_I_port and STB_I_port and ACK_I_mem and enable_read;
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enable_count <= CYC_I_port and STB_I_port and ACK_I_mem and enable_read;
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|
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finish_O <= s_finish;
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finish_O <= s_finish;
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s_finish <= '1' when address_counter = initial_address_I and init = '0' else
|
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'0';
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P_finish: process ( CLK_I, RST_I, address_counter, initial_address_I, load_I)
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-- P_finish: process ( CLK_I, RST_I, address_counter, initial_address_I, load_I)
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begin
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-- begin
|
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
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-- if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
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if RST_I = '1' then
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-- if RST_I = '1' then
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s_finish <= '1';
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-- --s_finish <= '0'; -- !! enable signal must be '0' until load
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init <= '0';
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-- init <= '0';
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elsif load_I = '1' then
|
-- elsif load_I = '1' then
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s_finish <= '0';
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-- --s_finish <= '0';
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init <= '1';
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-- init <= '1';
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elsif address_counter + 1 = initial_address_I then
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-- -- elsif address_counter + 1 = initial_address_I then
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s_finish <= '1';
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-- -- s_finish <= '1';
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init <= '0';
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-- -- init <= '0';
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else
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-- elsif enable_count = '1' then
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init <= '0';
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-- init <= '0';
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end if;
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-- end if;
|
end if;
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-- end if;
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end process;
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-- end process;
|
|
|
--------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------
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-- Address counter
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-- Address counter
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P_count: process(CLK_I, address_counter, enable_count, load_I)
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P_count: process(CLK_I, RST_I, address_counter, enable_count, load_I)
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begin
|
begin
|
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
|
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
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if load_I = '1' then
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if RST_I = '1' then
|
|
address_counter <= (others => '0');
|
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init <= '1';
|
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elsif load_I = '1' then
|
address_counter <= initial_address_I;
|
address_counter <= initial_address_I;
|
|
init <= '1';
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elsif enable_count = '1' and address_counter >= biggest_address_I then
|
elsif enable_count = '1' and address_counter >= biggest_address_I then
|
address_counter <= (others => '0');
|
address_counter <= (others => '0');
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elsif enable_count = '1' then
|
elsif enable_count = '1' then
|
address_counter <= address_counter + 1;
|
address_counter <= address_counter + 1;
|
|
init <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end architecture;
|
end architecture;
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No newline at end of file
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No newline at end of file
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