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[/] [modular_oscilloscope/] [trunk/] [hdl/] [ctrl/] [output_manager.vhd] - Diff between revs 54 and 55

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Rev 54 Rev 55
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----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
 
 
 
 
--==================================================================================================
--==================================================================================================
-- TO DO
-- TO DO
-- NO Speed up address_counter
-- · (NO) Speed up address_counter
-- OK Full test of new architecture
-- · (OK) Full test of new architecture
-- OK Fix default value of s_finish signal 
-- · (OK) Fix default value of s_finish signal 
-- ·  General speed up
-- ·  General speed up
--==================================================================================================
--==================================================================================================
 
 
 
 
library ieee;
library ieee;
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architecture ARCH22 of ctrl_output_manager is
architecture ARCH22 of ctrl_output_manager is
 
 
  signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1  downto 0);
  signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1  downto 0);
  signal enable_read: std_logic;
  signal enable_read: std_logic;
  signal enable_count: std_logic;
  signal enable_count: std_logic;
 
  signal enable_strobe: std_logic;
  signal s_finish: std_logic; -- register previous (and equal) to output
  signal s_finish: std_logic; -- register previous (and equal) to output
  signal init: std_logic;     -- register
  signal init: std_logic;     -- register
 
  signal same_address: std_logic;
 
 
begin
begin
 
 
  --------------------------------------------------------------------------------------------------
  --------------------------------------------------------------------------------------------------
  -- Wishbone signals
  -- Wishbone signals
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  WE_O_mem <= '0' ;
  WE_O_mem <= '0' ;
 
 
  --------------------------------------------------------------------------------------------------
  --------------------------------------------------------------------------------------------------
  -- Status signals  
  -- Status signals  
  -- there is an init signal because in the first read, address_counter may be = to pause_address_I
  -- there is an init signal because in the first read, address_counter may be = to pause_address_I
  enable_read <= '1'  when enable_I = '1' and  WE_I_port = '0' and s_finish = '0' and
  P_pause: process (CLK_I, RST_I, address_counter, pause_address_I)
                        (address_counter /= pause_address_I or init = '1')
  begin
 
    if CLK_I'event and CLK_I = '1' then
 
      if RST_I = '1' then
 
        same_address <= '0';
 
      elsif address_counter = pause_address_I then
 
        same_address <= '1';
 
      else
 
        same_address <= '0';
 
      end if;
 
    end if;
 
  end process;
 
 
 
  P_flags: process(CLK_I, RST_I, enable_I, enable_count, load_I)
 
  begin
 
    if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
 
      -- when enable is '0', finish_O must be 0 again
 
      if RST_I = '1' or enable_I = '0' then
 
        init <= '1';
 
        enable_strobe <= '0';
 
      elsif (load_I = '1' and enable_I = '1') then
 
        enable_strobe <= '1';
 
        init <= '1';
 
      elsif  enable_count = '1' then
 
        init <= '0';
 
      end if;
 
    end if;
 
  end process;
 
 
 
 
 
  enable_read <= '1'  when  WE_I_port = '0' and s_finish = '0' and
 
                            (same_address = '0' or init = '1') and enable_strobe = '1'
            else '0';
            else '0';
 
 
  enable_count <= CYC_I_port and STB_I_port and ACK_I_mem and enable_read;
  enable_count <= CYC_I_port and STB_I_port and ACK_I_mem and enable_read;
 
 
  finish_O <= s_finish;
 
  s_finish <= '1' when address_counter = initial_address_I and init = '0' else
  s_finish <= '1' when address_counter = initial_address_I and init = '0' else
              '0';
              '0';
 
  finish_O <= s_finish;
--   P_finish: process ( CLK_I, RST_I, address_counter, initial_address_I, load_I)
 
--   begin
 
--     if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
 
--       if RST_I = '1' then
 
--         --s_finish <= '0'; -- !! enable signal must be '0' until load
 
--         init <= '0';
 
--       elsif load_I = '1' then
 
--         --s_finish <= '0';
 
--         init <= '1';
 
--       -- elsif address_counter + 1 = initial_address_I then
 
--         -- s_finish <= '1';
 
--         -- init <= '0';
 
--       elsif enable_count = '1' then
 
--         init <= '0';
 
--       end if;
 
--     end if;
 
--   end process;
 
 
 
  --------------------------------------------------------------------------------------------------
  --------------------------------------------------------------------------------------------------
  -- Address counter
  -- Address counter
  P_count: process(CLK_I, RST_I, address_counter, enable_count, load_I)
  P_count: process(CLK_I, RST_I, address_counter, enable_count, load_I)
  begin
  begin
    if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
    if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
      if RST_I = '1' then
      if RST_I = '1' then
        address_counter <= (others => '0');
        address_counter <= (others => '0');
        init <= '1';
      elsif load_I = '1' and enable_I = '1' then
      elsif load_I = '1' then
 
        address_counter <= initial_address_I;
        address_counter <= initial_address_I;
        init <= '1';
 
      elsif enable_count = '1' and address_counter >= biggest_address_I then
      elsif enable_count = '1' and address_counter >= biggest_address_I then
        address_counter <= (others => '0');
        address_counter <= (others => '0');
      elsif  enable_count = '1' then
      elsif  enable_count = '1' then
        address_counter <= address_counter + 1;
        address_counter <= address_counter + 1;
        init <= '0';
 
      end if;
      end if;
    end if;
    end if;
  end process;
  end process;
 
 
end architecture;
end architecture;
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