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signal channels_I: std_logic_vector(15 downto 0);
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signal channels_I: std_logic_vector(15 downto 0);
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signal channel_number_O: std_logic_vector(3 downto 0);
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signal channel_number_O: std_logic_vector(3 downto 0);
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signal clk_I: std_logic;
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signal clk_I: std_logic;
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signal enable_I: std_logic;
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signal enable_I: std_logic;
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signal reset_I: std_logic;
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signal reset_I: std_logic;
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signal first_channel_O: std_logic;
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begin
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begin
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Instantiation of Stimulus.
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-- Instantiation of Stimulus.
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stimulus_0 : entity work.stimulus
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stimulus_0 : entity work.stimulus
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reset_I => reset_I
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reset_I => reset_I
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);
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);
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Instantiation of Model Under Test.
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-- Instantiation of Model Under Test.
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daq_0 : entity work.channel_selector
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chsel_0 : entity work.channel_selector
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port map (
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port map (
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channels_I => channels_I,
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channels_I => channels_I,
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channel_number_O => channel_number_O,
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channel_number_O => channel_number_O,
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clk_I => clk_I,
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clk_I => clk_I,
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enable_I => enable_I,
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enable_I => enable_I,
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reset_I => reset_I
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reset_I => reset_I,
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first_channel_O => first_channel_O
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);
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);
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end tbGeneratedCode;
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end tbGeneratedCode;
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No newline at end of file
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