| Line 1... |
Line 1... |
-------------------------------------------------------------------------------------------------100
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-------------------------------------------------------------------------------------------------100
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: trigger_manager.vhd
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--| File: ctrl_trigger_manager.vhd
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--| Version: 0.1
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--| Version: 0.1
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--| Tested in: Actel A3PE1500
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--| Tested in: Actel A3PE1500
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| CONTROL - Trigger manager
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--| CONTROL - Trigger manager
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| Line 31... |
Line 31... |
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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--use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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|
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|
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entity trigger_manager is
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entity ctrl_trigger_manager is
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generic (
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generic (
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MEM_ADD_WIDTH: integer := 14;
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MEM_ADD_WIDTH: integer := 14;
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DATA_WIDTH: integer := 10;
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DATA_WIDTH: integer := 10;
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CHANNELS_WIDTH: integer := 4
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CHANNELS_WIDTH: integer := 4
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);
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);
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| Line 58... |
Line 58... |
trigger_O: out std_logic;
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trigger_O: out std_logic;
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-- address when trigger plus offset
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-- address when trigger plus offset
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address_O: out std_logic_vector (MEM_ADD_WIDTH - 1 downto 0)
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address_O: out std_logic_vector (MEM_ADD_WIDTH - 1 downto 0)
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);
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);
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|
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end entity trigger_manager;
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end entity ctrl_trigger_manager;
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|
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architecture arch01_trigger of trigger_manager is
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architecture arch01_trigger of ctrl_trigger_manager is
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-- trigger process signals
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-- trigger process signals
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signal higher, higher_reg: std_logic;
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signal higher, higher_reg: std_logic;
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signal pre_trigger: std_logic;
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signal pre_trigger: std_logic;
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|
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-- signals for output address selection
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-- signals for output address selection
|
