| Line 1... |
Line 1... |
----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentina
|
--| UNSL - Argentina
|
--|
|
--|
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--| File: adq.vhd
|
--| File: daq.vhd
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--| Version: 0.1
|
--| Version: 0.1
|
--| Tested in: Actel A3PE1500
|
--| Tested in: Actel A3PE1500
|
--|-------------------------------------------------------------------------------------------------
|
--|-------------------------------------------------------------------------------------------------
|
--| Description:
|
--| Description:
|
--| Adquisition control module.
|
--| Acquisition control module.
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--| It drives the ADC chips.
|
--| It drives the ADC chip.
|
--|-------------------------------------------------------------------------------------------------
|
--|-------------------------------------------------------------------------------------------------
|
--| File history:
|
--| File history:
|
--| 0.01 | apr-2008 | First testing
|
--| 0.01 | apr-2008 | First testing
|
--| 0.10 | apr-2009 | First release
|
--| 0.10 | apr-2009 | First release
|
----------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------
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| Line 42... |
Line 42... |
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--use IEEE.STD_LOGIC_ARITH.all;
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--use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.NUMERIC_STD.ALL;
|
use IEEE.NUMERIC_STD.ALL;
|
--use work.adq_pgk.all;
|
--use work.adq_pgk.all;
|
|
|
entity adq is
|
entity daq is
|
generic (
|
generic (
|
DEFALT_CONFIG : std_logic_vector := "0000100000000000"
|
DEFALT_CONFIG : std_logic_vector := "0000100000000000"
|
-- bits 8 a 0 clk_pre_scaler
|
-- bits 8 a 0 clk_pre_scaler
|
-- bits 9 clk_pre_scaler_ena
|
-- bits 9 clk_pre_scaler_ena
|
-- bit 10 adc_sleep
|
-- bit 10 adc_sleep
|
| Line 75... |
Line 75... |
STB_I: in std_logic;
|
STB_I: in std_logic;
|
WE_I: in std_logic;
|
WE_I: in std_logic;
|
DAT_O: out std_logic_vector (15 downto 0);
|
DAT_O: out std_logic_vector (15 downto 0);
|
ACK_O: out std_logic
|
ACK_O: out std_logic
|
);
|
);
|
end adq;
|
end daq;
|
|
|
|
|
architecture beh1 of adq is
|
architecture beh1 of daq is
|
-- Tipos
|
-- Tipos
|
type data_array is array(0 to 2) of std_logic_vector(15 downto 0);
|
type data_array is array(0 to 2) of std_logic_vector(15 downto 0);
|
|
|
|
|
-- type arr is array(0 to 3) of std_logic_vector(15 downto 0);
|
-- type arr is array(0 to 3) of std_logic_vector(15 downto 0);
|
