| Line 1... |
Line 1... |
----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentina
|
--| UNSL - Argentina
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--|
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--|
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--| File: daq.vhd
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--| File: daq.vhd
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--| Version: 0.1
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--| Version: 0.40
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--| Tested in: Actel A3PE1500
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--| Tested in: Actel A3PE1500
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| Acquisition control module.
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--| Acquisition control module.
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--| It drives the ADC chip.
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--| It drives the ADC chip.
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.01 | apr-2008 | First testing
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--| 0.01 | apr-2008 | First testing
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--| 0.10 | apr-2009 | First release
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--| 0.10 | apr-2009 | First release
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--| 0.40 | jul-2009 | Added a read flag for each channel and adc_clk_I input
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright ® 2009, Facundo Aguilera.
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--| Copyright ® 2009, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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--| Wishbone Rev. B.3 compatible
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--| Wishbone Rev. B.3 compatible
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--==================================================================================================
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-- TODO
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-- · Access to both channels in consecutive reads
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--==================================================================================================
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--| TODO:
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--| Access to both channels in consecutive reads
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-- Esta primera versión está realizada específicamente para controlar el ADC AD9201. Otras
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-- Esta primera versión está realizada específicamente para controlar el ADC AD9201. Otras
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-- versiones podrán ser más genéricas.
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-- versiones podrán ser más genéricas.
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| Line 47... |
Line 51... |
entity daq is
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entity daq is
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generic (
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generic (
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DEFALT_CONFIG : std_logic_vector := "0000100000000000"
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DEFALT_CONFIG : std_logic_vector := "0000100000000000"
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-- bits 8 a 0 clk_pre_scaler
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-- bits 8 a 0 clk_pre_scaler
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-- bits 9 clk_pre_scaler_ena
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-- bits 9 clk_pre_scaler_ena
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-- bit 10 adc_sleep
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-- bit 10 adc sleep
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-- bit 11 adc_chip_sel
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-- bit 11 adc_chip_sel
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-- bits 12 a 15 sin usar
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-- bits 12 a 15 sin usar
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|
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-- si clk_pre_scaler_ena = 1
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-- si clk_pre_scaler_ena = 1
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-- frecuencia_adc = frecuencia_wbn / ((clk_pre_scaler+1)*2)
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-- frecuencia_adc = frecuencia_wbn / ((clk_pre_scaler+1)*2)
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-- sino frecuencia_adc = frecuencia_wbn
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-- sino frecuencia_adc = frecuencia_wbn
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);
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);
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port(
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port(
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-- Externo
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-- Externo
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adc_data: in std_logic_vector (9 downto 0);
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adc_data_I: in std_logic_vector (9 downto 0);
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adc_sel: out std_logic;
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adc_sel_O: out std_logic;
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adc_clk: out std_logic;
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adc_clk_O: out std_logic;
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adc_sleep: out std_logic;
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adc_sleep_O: out std_logic;
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adc_chip_sel: out std_logic;
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adc_chip_sel_O: out std_logic;
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-- Interno
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-- Interno
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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| Line 73... |
Line 77... |
ADR_I: in std_logic_vector (1 downto 0);
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ADR_I: in std_logic_vector (1 downto 0);
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CYC_I: in std_logic;
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CYC_I: in std_logic;
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STB_I: in std_logic;
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STB_I: in std_logic;
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WE_I: in std_logic;
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WE_I: in std_logic;
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DAT_O: out std_logic_vector (15 downto 0);
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DAT_O: out std_logic_vector (15 downto 0);
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ACK_O: out std_logic
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ACK_O: out std_logic;
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adc_clk_I: std_logic
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);
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);
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end daq;
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end daq;
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architecture beh1 of daq is
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architecture archdaq2 of daq is
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-- Tipos
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-- Tipos
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type data_array is array(0 to 2) of std_logic_vector(15 downto 0);
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type config_array is array(0 to 2) of std_logic_vector(15 downto 0);
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|
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-- type arr is array(0 to 3) of std_logic_vector(15 downto 0);
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-- type arr is array(0 to 3) of std_logic_vector(15 downto 0);
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--
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--
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-- signal arr_a : arr;
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-- signal arr_a : arr;
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| Line 92... |
Line 98... |
-- ....
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-- ....
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-- arr_a(0) <= vec_0;
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-- arr_a(0) <= vec_0;
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-- arr_a(1) <= vec_1;
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-- arr_a(1) <= vec_1;
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-- ....
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-- ....
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-- Registros de configuración
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type data_array is array(0 to 1) of std_logic_vector(adc_data_I'length - 1 downto 0);
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-- Registers
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signal config: std_logic_vector (15 downto 0);
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signal config: std_logic_vector (15 downto 0);
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signal selector: data_array;
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signal count: std_logic_vector (8 downto 0);
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signal channel_data: data_array;
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signal read_flag_adc: std_logic_vector (1 downto 0);
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signal read_flag_wb: std_logic_vector (1 downto 0);
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-- The biggest limit must be the channels number (-1)
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-- There are two clocks becouse there are two clocks
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|
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-- Registros
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-- Signals
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signal count: std_logic_vector (9 downto 0);
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signal selector: config_array;
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|
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-- Señales
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signal s_adc_clk, s_adc_sleep, s_adc_chip_sel: std_logic; -- previous to outputs
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signal s_adc_clk, s_adc_sleep, s_adc_chip_sel: std_logic;
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signal reduced_clk, same_clk: std_logic;
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signal data_ack_ready: std_logic; -- habilita confirmación de datos
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signal data_ack_ready: std_logic; -- habilita confirmación de datos
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signal conf_ack_ready: std_logic; -- habilita confirmación de escritura de configuración
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signal conf_ack_ready: std_logic; -- habilita confirmación de escritura de configuración
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signal clk_pre_scaler: std_logic_vector (8 downto 0);
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signal clk_pre_scaler: std_logic_vector (8 downto 0);
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signal clk_pre_scaler_ena: std_logic;
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signal clk_pre_scaler_ena: std_logic;
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signal channel_sel: std_logic_vector(0 downto 0); -- max limit must be the number of channels
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signal count_reset: std_logic;
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signal count_max: std_logic;
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--signal clk_enable: std_logic_vector (9 downto 0);
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--signal clk_enable: std_logic_vector (9 downto 0);
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begin
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begin
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Asignaciones
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-- Asignaciones
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---- Comunicación interna (Wishbone)
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---- Internal
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selector(0) <= config;
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selector(0) <= (config'length - 1 downto adc_data_I'length => '0' ) &
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selector(1) <= (config'length - 1 downto adc_data'length => '0' ) & adc_data;
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channel_data(conv_integer(channel_sel));
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selector(2) <= (config'length - 1 downto adc_data'length => '0' ) & adc_data;
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selector(1) <= (config'length - 1 downto adc_data_I'length => '0' ) &
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--selector(3) <= (others => '0' ); -- Sin usar
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channel_data(conv_integer(channel_sel));
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selector(2) <= config;
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--selector(3) <= (others => '0' ); -- Unassigned
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---- Registro de configuración config
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---- Config register
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clk_pre_scaler <= config(8 downto 0);
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clk_pre_scaler <= config(8 downto 0);
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clk_pre_scaler_ena <= config(9);
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clk_pre_scaler_ena <= config(9);
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s_adc_sleep <= config(10);
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s_adc_sleep <= config(10);
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s_adc_chip_sel <= config(11);
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s_adc_chip_sel <= config(11);
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-- sin asignar <= config(13); para usar en otras implementaciones
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-- Unassigned <= config(13);
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-- sin asignar <= config(14);
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-- Unassigned <= config(14);
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-- sin asignar <= config(15);
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-- Unassigned <= config(15);
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---- Comunicación externa (AD)
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---- External communication (AD)
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adc_sleep <= s_adc_sleep;
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adc_sleep_O <= s_adc_sleep;
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adc_chip_sel <= s_adc_chip_sel;
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adc_chip_sel_O <= s_adc_chip_sel;
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Generación de adc_clk
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-- Generación de adc_clk_O
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process (CLK_I, clk_pre_scaler,RST_I,count, clk_pre_scaler_ena)
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count_max <= '1' when count >= clk_pre_scaler else '0';
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count_reset <= RST_I or count_max or not(clk_pre_scaler_ena);
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P_count: process (adc_clk_I, count, count_reset)
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begin
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begin
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if RST_I = '1' then
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if adc_clk_I'event and adc_clk_I = '1' then
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if count_reset = '1' then
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count <= (others => '0');
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count <= (others => '0');
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s_adc_clk <= '0';
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else
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elsif clk_pre_scaler_ena = '1' then
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if CLK_I'event and CLK_I = '1' then
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count <= count + 1;
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count <= count + 1;
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if count = clk_pre_scaler then
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s_adc_clk <= not(s_adc_clk);
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count <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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else
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end process;
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count <= (others => '0');
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s_adc_clk <= CLK_I;
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P_adcclk: process (adc_clk_I, RST_I, clk_pre_scaler_ena)
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begin
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if adc_clk_I'event and adc_clk_I = '1' then
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if RST_I = '1' or clk_pre_scaler_ena = '0' then
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reduced_clk <= '0';
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elsif count_max = '1' then
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reduced_clk <= not(reduced_clk);
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end if;
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end if;
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end if;
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-- OLD
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-- if RST_I = '1' then
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-- count <= (others => '0');
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-- s_adc_clk <= '0';
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-- elsif clk_pre_scaler_ena = '1' then
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-- if CLK_I'event and CLK_I = '1' then
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-- count <= count + 1;
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-- if count = clk_pre_scaler then
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-- s_adc_clk <= not(s_adc_clk);
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-- count <= (others => '0');
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-- end if;
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-- end if;
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-- else
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-- count <= (others => '0');
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-- s_adc_clk <= CLK_I;
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-- end if;
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end process;
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end process;
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adc_clk <= s_adc_clk;
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same_clk <= adc_clk_I;
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with clk_pre_scaler_ena select
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s_adc_clk <= reduced_clk when '1',
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same_clk when others;
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adc_clk_O <= s_adc_clk;
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Generación ack
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-- Generación ack
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-- When ADR_I(1) = '1', master will be accessing to confing register.
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|
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ACK_O <= CYC_I and STB_I and (data_ack_ready or conf_ack_ready);
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ACK_O <= CYC_I and STB_I and (data_ack_ready or conf_ack_ready);
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data_ack_ready <= '1' when (unsigned(count) = 0 and WE_I = '0' and unsigned(ADR_I) /= 0 and s_adc_clk = '1')
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or (clk_pre_scaler_ena /= '1')
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else
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'0';
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-- count = 0 asegura que el dato actual ya fue leído
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conf_ack_ready <= '1' when unsigned(ADR_I) = 0 else
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data_ack_ready <= (read_flag_wb(conv_integer(channel_sel)) xnor read_flag_adc(conv_integer(channel_sel))) and not(WE_I);
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'0';
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conf_ack_ready <= ADR_I(1);
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Selección de canal
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-- Channel selection
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adc_sel <= '1' when unsigned(ADR_I) = 2 else -- selecciona canal Q
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'0'; -- selecciona canal I
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-- channel_data(0) --> Q channel
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-- channel_data(1) --> I channel (of ADC AD9201)
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channel_sel(0) <= ADR_I(0);
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P_dataread: process (s_adc_clk, adc_data_I)
|
|
begin
|
|
if s_adc_clk'event and s_adc_clk = '1' then
|
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channel_data(0) <= adc_data_I;
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end if;
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if s_adc_clk'event and s_adc_clk = '0' then
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channel_data(1) <= adc_data_I;
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end if;
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end process;
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|
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P_flags: process (s_adc_clk, CLK_I, CYC_I, STB_I, ADR_I, read_flag_adc, read_flag_wb,channel_sel)
|
|
begin
|
|
|
|
if s_adc_clk'event and s_adc_clk = '1' then
|
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read_flag_adc(0) <= read_flag_wb(0);
|
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end if;
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|
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if s_adc_clk'event and s_adc_clk = '0' then
|
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read_flag_adc(1) <= read_flag_wb(1);
|
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end if;
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|
|
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if CLK_I'event and CLK_I = '1' then
|
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if RST_I = '1' then
|
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read_flag_wb <= (others => '0');
|
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--read_flag_adc <= (others => '1');
|
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elsif CYC_I = '1' and STB_I = '1' and ADR_I(1) = '0' then -- read_flag(conv_integer(channel_sel)) = '0' and
|
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read_flag_wb(conv_integer(channel_sel)) <= not(read_flag_adc(conv_integer(channel_sel)));
|
|
end if;
|
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end if;
|
|
|
|
|
|
|
|
end process;
|
|
|
|
adc_sel_O <= s_adc_clk;
|
|
|
--------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------
|
-- Lectura y escritura de datos
|
-- Lectura y escritura de datos
|
---- Generación de DAT_O
|
---- Generación de DAT_O
|
DAT_O <= selector(conv_integer(ADR_I));
|
DAT_O <= selector(conv_integer(ADR_I));
|
|
|
---- Almacenado de registro de configuración
|
---- Almacenado de registro de configuración
|
process (CLK_I, ADR_I, RST_I, DAT_I)
|
P_output: process (CLK_I, ADR_I, RST_I, DAT_I)
|
begin
|
begin
|
|
|
if CLK_I'event and CLK_I = '1' then
|
if CLK_I'event and CLK_I = '1' then
|
if RST_I = '1' then
|
if RST_I = '1' then
|
config <= DEFALT_CONFIG;
|
config <= DEFALT_CONFIG;
|
elsif WE_I = '1' and CYC_I = '1' and STB_I = '1' then
|
elsif WE_I = '1' and CYC_I = '1' and STB_I = '1' then
|
if unsigned(ADR_I) = 0 then
|
if unsigned(ADR_I) = 2 then
|
config <= DAT_I;
|
config <= DAT_I;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
|
|
|
|
end architecture beh1;
|
|
No newline at end of file
|
No newline at end of file
|
|
end architecture archdaq2;
|
No newline at end of file
|
No newline at end of file
|
