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-- eppwbn.vhd
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--|-----------------------------------------------------------------------------
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--| UNSL - Modular Oscilloscope
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--|
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--| File: eppwbn_wbn_side.vhd
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--| Version: 0.10
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--| Targeted device: Actel A3PE1500
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--|-----------------------------------------------------------------------------
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--| Description:
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--| EPP - Wishbone bridge.
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--| This instantiate all the other modules. The TOP
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--------------------------------------------------------------------------------
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--| File history:
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--| 0.01 | dic-2008 | First testing release
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--------------------------------------------------------------------------------
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--| Copyright Facundo Aguilera 2008
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--| GPL
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-- Bloque completo
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-- Bloque completo
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use work.eppwbn_pgk.all;
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entity eppwbn is
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entity eppwbn is
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port(
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port(
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-- Externo
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-- Externo
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284 ECP/EPP (Compatibiliy)
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
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-- HostClk/nWrite
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-- HostClk/nWrite
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Data: inout std_logic_vector (7 downto 0); --AD8..1 (Data1..Data8)
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Data: inout std_logic_vector (7 downto 0); --AD8..1 (Data1..Data8)
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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PError: out std_logic; -- AckData/nAckReverse
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PError: out std_logic; -- AckData/nAckReverse
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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nInit: in std_logic; -- nReverseRequest
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nInit: in std_logic; -- nReverseRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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HostLogicH: in std_logic; -- (Host Logic High)
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-- Interno
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-- Interno
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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DAT_I: in std_logic_vector (15 downto 0);
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DAT_I: in std_logic_vector (7 downto 0);
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ADR_I: in std_logic_vector (15 downto 0);
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DAT_O: out std_logic_vector (7 downto 0);
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DAT_O: out std_logic_vector (15 downto 0);
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ADR_O: out std_logic_vector (7 downto 0);
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ADR_O: out std_logic_vector (15 downto 0);
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CYC_O: out std_logic;
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CYC_I: in std_logic;
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STB_O: out std_logic;
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ACK_O: out std_logic;
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ACK_I: in std_logic ;
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WE_I: in std_logic;
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WE_O: out std_logic
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);
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);
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end eppwbn;
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end eppwbn;
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architecture wbn16epp8 of eppwbn
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architecture structural of eppwbn is
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------------------------------------------------------------------------------
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entity eppwbn_ctrl is
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-- Señales
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port(
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signal s_epp_mode: std_logic_vector (1 downto 0);
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284-2000,
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signal s_rst_pp: std_logic;
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Data: in std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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signal s_wb_Busy: std_logic;
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PError: out std_logic; -- AckData/nAckReverse
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signal s_wb_nAutoFd: std_logic;
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Sel: out std_logic; -- XFlag (Select). Select no puede usarse
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signal s_wb_nSelectIn: std_logic;
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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signal s_wb_nStrobe: std_logic;
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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nInit: in std_logic; -- nReverseRequest
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signal s_ctr_nAck: std_logic;
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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signal s_ctr_PError: std_logic;
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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signal s_ctr_Sel: std_logic;
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signal s_ctr_nFault: std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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signal s_ctr_nAutoFd: std_logic;
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signal s_ctr_nSelectIn: std_logic;
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signal s_ctr_nStrobe: std_logic;
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rst_pp: out std_logic; -- generador de reset desde la interfaz del puerto paralelo
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epp_mode: out std_logic_vector (1 downto 0) -- indicador de modo de comunicaci?n epp
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);
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end entity eppwbn_ctrl;
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entity eppwbn_epp_side is
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port(
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epp_mode: in std_logic_vector (1 downto 0);-- indicador de modo de comunicaci?n epp
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ctr_nAck: in std_logic; -- PtrClk/PeriphClk/Intr
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ctr_PError: in std_logic; -- AckData/nAckReverse
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ctr_Sel: in std_logic; -- XFlag (Select). Select no puede usarse
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ctr_nFault: in std_logic; -- nDataAvail/nPeriphRequest
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ctr_nAutoFd: out std_logic; -- HostBusy/HostAck/nDStrb
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ctr_nSelectIn: out std_logic; -- 1284 Active/nAStrb
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ctr_nStrobe: out std_logic; -- HostClk/nWrite
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wb_Busy: in std_logic; -- PtrBusy/PeriphAck/nWait
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wb_nAutoFd: out std_logic; -- HostBusy/HostAck/nDStrb
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wb_nSelectIn: out std_logic; -- 1284 Active/nAStrb
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wb_nStrobe: out std_logic; -- HostClk/nWrite
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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PError: out std_logic; -- AckData/nAckReverse
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Sel: out std_logic; -- XFlag (Select). Select no puede usarse
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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Busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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begin
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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nStrobe: in std_logic -- HostClk/nWrite
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);
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end entity eppwbn_epp_side;
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entity eppwbn_wbn_side is
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-- Conexión del módulo de control
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port(
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U1: eppwbn_ctrl
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inStrobe: in std_logic; -- HostClk/nWrite
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port map (
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iData: inout std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
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nStrobe => s_ctr_nStrobe,
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iBusy: out std_logic; -- PtrBusy/PeriphAck/nWait
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Data => Data,
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inAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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nAck => s_ctr_nAck,
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inSelectIn: in std_logic; -- 1284 Active/nAStrb
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PError => s_ctr_PError,
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Sel => s_ctr_Sel,
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nAutoFd => s_ctr_nAutoFd,
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PeriphLogicH => PeriphLogicH,
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nInit => nInit,
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nFault => s_ctr_nFault,
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nSelectIn => s_ctr_nSelectIn,
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RST_I: in std_logic;
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RST_I => RST_I,
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CLK_I: in std_logic;
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CLK_I => CLK_I,
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DAT_I: in std_logic_vector (7 downto 0);
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DAT_O: out std_logic_vector (7 downto 0);
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ADR_O: out std_logic_vector (7 downto 0);
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CYC_O: out std_logic;
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STB_O: out std_logic;
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ACK_I: in std_logic ;
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WE_O: out std_logic;
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rst_pp: in std_logic -- reset desde la interfaz del puerto paralelo
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rst_pp => s_rst_pp,
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epp_mode => s_epp_mode
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);
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);
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-- Conexión de módulo multiplexor
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U2: eppwbn_epp_side
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port map (
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epp_mode => s_epp_mode,
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ctr_nAck => s_ctr_nAck,
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ctr_PError => s_ctr_PError,
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ctr_Sel => s_ctr_Sel,
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ctr_nFault => s_ctr_nFault,
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ctr_nAutoFd => s_ctr_nAutoFd,
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ctr_nSelectIn => s_ctr_nSelectIn,
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ctr_nStrobe=> s_ctr_nStrobe,
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wb_Busy => s_wb_Busy,
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wb_nAutoFd => s_wb_nAutoFd,
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wb_nSelectIn => s_wb_nSelectIn,
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wb_nStrobe => s_wb_nStrobe,
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nAck => nAck,
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PError => PError,
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Sel => Sel,
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nFault => nFault,
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Busy => Busy,
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nAutoFd => nAutoFd,
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nSelectIn => nSelectIn,
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nStrobe => nStrobe
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);
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begin
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-- Conexión del módulo de comunicación con interfaz wishbone
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U3: eppwbn_wbn_side
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port map(
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inStrobe => s_wb_nStrobe,
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iData => Data,
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iBusy => s_wb_Busy,
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inAutoFd => s_wb_nAutoFd,
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inSelectIn => s_wb_nSelectIn,
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RST_I => RST_I,
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CLK_I => CLK_I,
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DAT_I => DAT_I,
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DAT_O => DAT_O,
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ADR_O => ADR_O,
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CYC_O => CYC_O,
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STB_O => STB_O,
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ACK_I => ACK_I,
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WE_O => WE_O,
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rst_pp => s_rst_pp
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);
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end architecture;
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