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--|-----------------------------------------------------------------------------
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--|-----------------------------------------------------------------------------
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--| UNSL - Modular Oscilloscope
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--| UNSL - Modular Oscilloscope
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--|
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--|
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--| File: eppwbn_wbn_side.vhd
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--| File: eppwbn_wbn_side.vhd
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--| Version: 0.10
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--| Version: 0.01
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--| Targeted device: Actel A3PE1500
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--| Targeted device: Actel A3PE1500
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--|-----------------------------------------------------------------------------
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--|-----------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| This instantiate all the other modules. The TOP
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--| Instantiate all the other modules. The TOP file.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.01 | dic-2008 | First testing release
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--| 0.01 | dic-2008 | First release
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--| Copyright Facundo Aguilera 2008
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--| Copyright ® 2008, Facundo Aguilera.
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--| GPL
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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-- Bloque completo
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-- Bloque completo
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library IEEE;
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library IEEE;
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