| Line 1... |
Line 1... |
--|-----------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| UNSL - Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--|
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--|
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--| File: eppwbn_wbn_side.vhd
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--| File: eppwbn.vhd
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--| Version: 0.01
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--| Version: 0.1
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--| Targeted device: Actel A3PE1500
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--| Tested in: Actel APA300
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--|-----------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| Instantiate all the other modules. The TOP file.
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--| The top module for 8 bit wisbone data bus.
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--------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.01 | dic-2008 | First release
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--| 0.01 | dic-2008 | First release
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--------------------------------------------------------------------------------
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--| 0.10 | feb-2009 | Working
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----------------------------------------------------------------------------------------------------
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--| Copyright ® 2008, Facundo Aguilera.
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--| Copyright ® 2008, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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--| Wishbone Rev. B.3 compatible
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|
----------------------------------------------------------------------------------------------------
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-- Bloque completo
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-- Bloque completo
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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| Line 38... |
Line 44... |
PeriphLogicH: out std_logic; -- (Periph Logic High)
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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nInit: in std_logic; -- nReverseRequest
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nInit: in std_logic; -- nReverseRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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-- Interno
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-- Interno
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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DAT_I: in std_logic_vector (7 downto 0);
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DAT_I: in std_logic_vector (7 downto 0);
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DAT_O: out std_logic_vector (7 downto 0);
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DAT_O: out std_logic_vector (7 downto 0);
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| Line 77... |
Line 84... |
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begin
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begin
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-- Conexión del módulo de control
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-- Conexión del módulo de control
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U1: eppwbn_ctrl
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U1: eppwbn_ctrl
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port map (
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port map (
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nStrobe => s_ctr_nStrobe,
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nStrobe => s_ctr_nStrobe,
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Data => Data,
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Data => Data,
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