URL https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk

Subversion Repositories modular_oscilloscope

[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [eppwbn.vhd] - Diff between revs 19 and 22

Rev 19	Rev 22
Line 26...	Line 26...

`-- Bloque completo`	`-- Bloque completo`

`library IEEE;`	`library IEEE;`
`use IEEE.STD_LOGIC_1164.all;`	`use IEEE.STD_LOGIC_1164.all;`
`use work.eppwbn_pgk.all;`	`use work.eppwbn_pkg.all;`

`entity eppwbn is`	`entity eppwbn is`
`port(`	`port(`

	`-- TEMPORAL`
	`epp_mode_monitor: out std_logic_vector (1 downto 0);`



`-- Externo`	`-- Externo`
`nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284`	`nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284`
`-- HostClk/nWrite`	`-- HostClk/nWrite`
`Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)`	`Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)`
`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`	`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`
Line 84...	Line 90...




`begin`	`begin`

	`-- TEMPORAL`
	`epp_mode_monitor <= s_epp_mode;`


`-- Conexi�n del m�dulo de control`	`-- Conexi�n del m�dulo de control`
`U1: eppwbn_ctrl`	`U1: eppwbn_ctrl`
`port map (`	`port map (`
`nStrobe => s_ctr_nStrobe,`	`nStrobe => s_ctr_nStrobe,`
`Data => Data,`	`Data => Data,`