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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: eppwbn.vhd
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--| File: eppwbn.vhd
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--| Version: 0.1
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--| Version: 0.1
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--| Tested in: Actel APA300
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--| Tested in: Actel APA300
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--| Tested in: Actel A3PE1500
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| The top module for 8 bit wisbone data bus.
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--| The top module for 8 bit wisbone data bus.
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.01 | dic-2008 | First release
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--| 0.01 | dic-2008 | First release
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--| 0.10 | feb-2009 | Working
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--| 0.10 | feb-2009 | Working
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright ® 2008, Facundo Aguilera.
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--| Copyright © 2008, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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--| Wishbone Rev. B.3 compatible
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--| Wishbone Rev. B.3 compatible
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