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--| Description:
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--| Description:
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--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| The top module for 8 bit wisbone data bus.
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--| The top module for 8 bit wisbone data bus.
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.01 | dic-2008 | First release
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--| 0.10 | feb-2009 | Working
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--| 0.10 | feb-2009 | Working
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright © 2008, Facundo Aguilera.
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--| Copyright © 2008, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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entity eppwbn is
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entity eppwbn is
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port(
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port(
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-- TEMPORAL
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-- TEMPORAL
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epp_mode_monitor: out std_logic_vector (1 downto 0);
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--epp_mode_monitor: out std_logic_vector (1 downto 0);
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-- Externo
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-- Externo
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
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-- HostClk/nWrite
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-- HostClk/nWrite
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Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
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Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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nInit: in std_logic; -- nReverseRequest
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nInit: in std_logic; -- nReverseRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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-- Interno
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-- Interno
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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DAT_I: in std_logic_vector (7 downto 0);
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DAT_I: in std_logic_vector (7 downto 0);
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DAT_O: out std_logic_vector (7 downto 0);
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DAT_O: out std_logic_vector (7 downto 0);
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signal s_ctr_nAutoFd: std_logic;
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signal s_ctr_nAutoFd: std_logic;
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signal s_ctr_nSelectIn: std_logic;
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signal s_ctr_nSelectIn: std_logic;
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signal s_ctr_nStrobe: std_logic;
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signal s_ctr_nStrobe: std_logic;
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begin
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begin
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-- TEMPORAL
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-- TEMPORAL
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epp_mode_monitor <= s_epp_mode;
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--epp_mode_monitor <= s_epp_mode;
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-- Conexión del módulo de control
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-- Conexión del módulo de control
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U1: eppwbn_ctrl
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U1: eppwbn_ctrl
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port map (
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port map (
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