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end eppwbn;
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end eppwbn;
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architecture wbn16epp8 of eppwbn
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architecture wbn16epp8 of eppwbn
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entity eppwbn_ctrl is
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port(
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284-2000,
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Data: in std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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PError: out std_logic; -- AckData/nAckReverse
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Sel: out std_logic; -- XFlag (Select). Select no puede usarse
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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nInit: in std_logic; -- nReverseRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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RST_I: in std_logic;
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CLK_I: in std_logic;
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rst_pp: out std_logic; -- generador de reset desde la interfaz del puerto paralelo
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epp_mode: out std_logic_vector (1 downto 0) -- indicador de modo de comunicaci?n epp
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);
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end entity eppwbn_ctrl;
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entity eppwbn_epp_side is
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port(
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epp_mode: in std_logic_vector (1 downto 0);-- indicador de modo de comunicaci?n epp
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ctr_nAck: in std_logic; -- PtrClk/PeriphClk/Intr
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ctr_PError: in std_logic; -- AckData/nAckReverse
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ctr_Sel: in std_logic; -- XFlag (Select). Select no puede usarse
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ctr_nFault: in std_logic; -- nDataAvail/nPeriphRequest
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ctr_nAutoFd: out std_logic; -- HostBusy/HostAck/nDStrb
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ctr_nSelectIn: out std_logic; -- 1284 Active/nAStrb
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ctr_nStrobe: out std_logic; -- HostClk/nWrite
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wb_Busy: in std_logic; -- PtrBusy/PeriphAck/nWait
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wb_nAutoFd: out std_logic; -- HostBusy/HostAck/nDStrb
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wb_nSelectIn: out std_logic; -- 1284 Active/nAStrb
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wb_nStrobe: out std_logic; -- HostClk/nWrite
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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PError: out std_logic; -- AckData/nAckReverse
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Sel: out std_logic; -- XFlag (Select). Select no puede usarse
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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Busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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nStrobe: in std_logic -- HostClk/nWrite
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);
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end entity eppwbn_epp_side;
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entity eppwbn_wbn_side is
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port(
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inStrobe: in std_logic; -- HostClk/nWrite
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iData: inout std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
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iBusy: out std_logic; -- PtrBusy/PeriphAck/nWait
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inAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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inSelectIn: in std_logic; -- 1284 Active/nAStrb
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RST_I: in std_logic;
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CLK_I: in std_logic;
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DAT_I: in std_logic_vector (7 downto 0);
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DAT_O: out std_logic_vector (7 downto 0);
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ADR_O: out std_logic_vector (7 downto 0);
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CYC_O: out std_logic;
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STB_O: out std_logic;
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ACK_I: in std_logic ;
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WE_O: out std_logic;
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rst_pp: in std_logic -- reset desde la interfaz del puerto paralelo
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);
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begin
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begin
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No newline at end of file
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No newline at end of file
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