URL https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk

Subversion Repositories modular_oscilloscope

[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [eppwbn_16bit.vhd] - Diff between revs 19 and 22

Rev 19	Rev 22
Line 25...	Line 25...

`-- Bloque completo 16 bit`	`-- Bloque completo 16 bit`

`library IEEE;`	`library IEEE;`
`use IEEE.STD_LOGIC_1164.all;`	`use IEEE.STD_LOGIC_1164.all;`
`use work.eppwbn_pgk.all;`	`use work.eppwbn_pkg.all;`

`entity eppwbn_16bit is`	`entity eppwbn_16bit is`
`port(`	`port(`
`-- Externo`	`-- Externo`
`nStrobe: in std_logic; -- HostClk/nWrite`	`nStrobe: in std_logic; -- HostClk/nWrite`
Line 52...	Line 52...
`DAT_O: out std_logic_vector (15 downto 0);`	`DAT_O: out std_logic_vector (15 downto 0);`
`ADR_O: out std_logic_vector (7 downto 0);`	`ADR_O: out std_logic_vector (7 downto 0);`
`CYC_O: out std_logic;`	`CYC_O: out std_logic;`
`STB_O: out std_logic;`	`STB_O: out std_logic;`
`ACK_I: in std_logic ;`	`ACK_I: in std_logic ;`
`WE_O: out std_logic`	`WE_O: out std_logic;`

	`-- TEMPORAL monitores`
	`epp_mode_monitor: out std_logic_vector(1 downto 0)`

`);`	`);`
`end eppwbn_16bit;`	`end eppwbn_16bit;`



Line 72...	Line 76...
`begin`	`begin`


`U_EPPWBN8: eppwbn`	`U_EPPWBN8: eppwbn`
`port map(`	`port map(`
	`-- TEMPORAL`
	`epp_mode_monitor => epp_mode_monitor,`


`-- To EPP interface`	`-- To EPP interface`
`nStrobe => nStrobe,`	`nStrobe => nStrobe,`
`Data => Data,`	`Data => Data,`
`nAck => nAck,`	`nAck => nAck,`
`busy => busy,`	`busy => busy,`