URL https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk

Subversion Repositories modular_oscilloscope

[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [eppwbn_16bit_test.vhd] - Diff between revs 41 and 57

Rev 41	Rev 57
Line 126...	Line 126...
`-- WE_I => WE_O_master`	`-- WE_I => WE_O_master`
`-- );`	`-- );`


`s_to_mem_ADR_I_a <= (13 downto 8 => '0') & ADR_O_master;`	`s_to_mem_ADR_I_a <= (13 downto 8 => '0') & ADR_O_master;`

`SL_MEM2: dual_port_memory_wb port map(`	`SL_MEM2: dual_port_memory_wb port map(`
`-- Puerto A`	`-- Puerto A`
`RST_I_a => s_not_rst,`	`RST_I_a => s_not_rst,`
`CLK_I_a => clk_pll,`	`CLK_I_a => clk_pll,`
`DAT_I_a => DAT_O_master,`	`DAT_I_a => DAT_O_master,`
Line 175...	Line 176...
`DAT_O => DAT_O_master,`	`DAT_O => DAT_O_master,`
`ADR_O => ADR_O_master,`	`ADR_O => ADR_O_master,`
`CYC_O => CYC_O_master,`	`CYC_O => CYC_O_master,`
`STB_O => STB_O_master,`	`STB_O => STB_O_master,`
`ACK_I => ACK_I_master,`	`ACK_I => ACK_I_master,`
`WE_O => WE_O_master,`	`WE_O => WE_O_master`

`-- MONITORES`	`-- MONITORES`
`-- TEMPORAL`	`-- TEMPORAL`
`epp_mode_monitor => s_not_epp_mode`	`--epp_mode_monitor => s_not_epp_mode`
`);`	`);`



`PLL_0: component A3PE_pll`	`PLL_0: component A3PE_pll`